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A PENNWELL PUBLICATION: DECEMBER 1992 


COMPUTER 


Data I/O's Tom Clark on: 


FPGA design FOR ELECTRONIC ENGINEERS & ENGINEERING MANAGERS 


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-7-~-§CSI DEVICE 
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just about that easily. 


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CIRCLE NO. 1 


Innovative Technology 
In System Packaging 


One Thing 


Separates a Great System 
Enclosure from a Good One. 


It’s the innovative application of 
cutting-edge technology to your 
specific requirements. It’s what we 
do at Electronic Solutions. 

If you’re the engineer responsible 
for the system packaging, you have 
your hands full dealing with power 
distribution, cooling, and safety con- 
cerns such as UL, CSA and VDE 
approvals. That’s where Electronic 
Solutions can make your job easier! 
You can rely on our experience and 
expertise to quickly resolve the 
design issues you're facing —at a 
price that even your bean counters 
will be pleased with. 

Airflow testing. Our in-house 
airflow /temperature testing facility 


allows us to carefully examine the 
environment i/side a system enclo- 
sure, testing the effects of wire har- 
ness placement, fan size and loca- 
tion, and the characteristics of the 
airflow path itself. We can even test 
your complete system to fine tune 
air direction, cool hot spots, and 
reduce audible fan noise and power 
consumption. 

Safety Agency Approvals. 
Bypass the costly maze of paper- 
work and testing! We can provide 
enclosures that are already UL listed, 
CSA certified, and GS approved 
through TUV certification. That big 
step allows you to install recognized 
boards and peripherals and win 


VMEbus 
VXI bus 


Tabletop, 
Rackmount, 
Sun bus DeskMate, 
Mixed buses Bellcore and 
Proprietary buses Custom 
Muttibus I Designs 
Multibus II 

Futurebus+ 


CIRCLE NO. 2 


agency approval of your finished 
system with no additional effort or 
cost! As a self-testing facility for the 
agencies, we’re equipped to handle 
every aspect of certification to 
reduce your costs and shorten your 
time to market. 

EMI/RFI Testing. We subject our 
enclosures to in-house testing per 
MIL-STD-285, providing an attenua- 
tion profile of each unit. When it 
comes time for you to pursue FCC 
or VDE approval of your system, we 
can perform these tests for you and 
resolve any problems immediately. 

Whether it’s off-the-shelf or 
something special that’s off-the- 
drawing board, there’s only one way 
to get the enclosure that’s just right 
for your system. That's to call 
Electronic Solutions and put our 
experience to work for you. 


Electronic 
y, Solutions 


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ZeER 


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The New Dual '040 VME SBC: 


Faster, More Efficient and Lower Cost 
Than Any Multi-board Solution 


Get on-board multiprocessing and an astounding 
40 MIPS throughput, when you power your system 
with Synergy's new SV420 single-slot SBC. The 
$V420's dual-CPU design means you'll need fewer 
boards in your VME chassis, with no VMEbus 
bandwidth bottlenecks between the '040s, and system- 
wide cost saving of more than 40%. 

And even if you don't need multiprocessing right 
now, the SV420 still puts you out front. Use the 
second '040 as a super-smart DMA controller. When 
combined with the SV420's 
66 MByte/sec VME64* 
circuitry, nothing 
communicates faster over 
the VMEbus. 

Add even more on- 
board power by selecting 
from Synergy's big list of 


Over a dozen smart, powerful 1/0 
modules fit Synergy's '020, '030, 
'040 and Dual '040 SBC's. 


high-performance, intelligent plug-on I/O modules — 
such as our latest Super-VSB module offering 

40+ MB/sec over the VSB bus. 
Or choose another module, from Pa 


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nes ae 


a T1/E1 controller to a super-fast Ei 
graphics engine, that plugs onto 
any Synergy SBC. 

Better yet, just tell us what you 


need. We're the company you can 
talk to about your VME system 
design problems. You'll find that we listen and 
deliver (every Synergy 1/O module on our list 
started as a customer request). We mean 
business when we say customer support is our 
most important mission. 

So if you want to be out front in system 
performance, just be up front with Synergy. 
Call us today. 


microsystems 
Synergy Microsystems, Inc. 

179 Calle Magdalena, Encinitas, CA 92024 
(619) 753-2191 FAX: 619-753-0903 


CIRCLE NO. 3 


A PENNWELL PUBLICATION VOL 31, NO 12 / DECEMBER 1992 


COMPUTER ‘Technology 


and Design 
Directions 


FOR ELECTRONIC ENGINEERS & ENGINEERING MANAGERS 


Designers of 
embedded systems 
can enjoy increased 
compute power, 
higher integration 
and high-level pro- 
gramming lan- 
guages if they wish 
for, and can use, 32- 
bit microcontrollers 
in their next-genera- 


tion designs............ 91 
Ecitorlaliesceecsc 22 
Calendar ................ 24 


Advertiser Index.....143 


COMING NEXT 
MONTH 


Verilog and VHDL 


DSP development | 
tools | 


Disk drive control- | 
lers and ICs 
C cross compilers 


Networking 


ENEWS BRIEFS 


MIPS forges ahead . . . Chorus spreads microkernel-based UNIX 

. . Benchmarks proposed for fuzzy logic . . . ViaLink helps 
QuickLogic cut FPGA prices . . . Vitesse prices GaAs ASICs to 
beat BICMOS... A kinder, gentler EDIF? . . . Modeling informa- 
tion comes online . . . PCI gets expansion connector . . . Stand- 
ards set for memory interface . . . 486 rivalry continues 
ATRPEASEHTECI ss cas eed ats evteresthis ts aetcserwraalsn uesnceanan tek aputons kegbinieownacase 10 


ETECHNOLOGY DIRECTIONS 


Integrated Circuits 

New clock chips are analgesic for run-length headaches ............ 34 
IEDIVI Ge LS TRIAVEINE ea seeuencstesvsss snesracesuneoeranediapeetaeasenueasmitassaee 40 
Analog Devices courts designers with open architecture DSP ......46 


Software & Development Tools 
Alliances to speed acceptance of fuzzy logic technology............. 52 


Computers & Subsystems 


HP debuts VME, realtime SOIUtIONS..............cccccesereceeeessteeeeseees 58 

Image processing gets price-performance boost...............0:6600 62 

CAE/CAD Tools 

No agreement on best way to link digital and analog 

SIMIC eM Stee tanta coy taser Sere tee, Se Rept Mec cee Aes eal 67 

ASICs & ASIC Design Tools 

EDA vendors push to boost top-down design productivity.......... 70 

ENEW PRODUCT DEVELOPMENTS iaae se eee 


©°0909000000 


CAE/CAD Design Tools 
Windows-based PCB tool suite boasts workstation 


2 
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Vvvvy 


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Rasocoosooo mE 


features 123 0090000000 


Software & Development Tools 
Hardware/software combo debuts for realtime design 


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Optimizing C compiler tightly coupled to realtime OS.............. 126 Prey 


oor 


Computers & Subsystems sje 
ACCESS.bus hardware released for industrial and sje 
COM MME Cla EMVIROMIMENIS veceoe-c.cde-seataeececestocerus sector eee cake 128 ie 
Intel beefs up Multibus line using 486 processors ................66+. 130 


Press <Left> or <Space> at the line starting point. 
Page 123 


CONTINUED ON PAGE 5 COMPUTER DESIGN 


DECEMBER 1992 3 


Seeking an affordable, 
high-performance development system? 
Our Lite’s at the end of the tunnel. 


It’s traditionally presented a 
pretty dark scenario, the quest 
for emulation and debugging tools 
that are integrated and proven. 
That are powerful and, perhaps 
most elusive, highly affordable. 

No more. At under $5,000, HMI’s 
new Lite development system, 
integrating real-time emu- 
lation with our renowned 
SourceGate high-level- 
language debugger, offers 
a brilliant end to the search. 
And lights up the industry with 
a new price/performance standard. 

Field proven by the thousands, 
SourceGate supports all major 


industry compilers: C, PASCAL and 
Ada. And the task is streamlined 
by menus, customizable windows, 
single stepping, and variable watch 
windows all controlled at the 
source code level. 

No dead-ends in emulators, either; 
the Lite series features multiple 
hardware breakpoints, 
full trace capabilities 

and dual ported RAM 
for real-time monitor of 
critical variables. And, you'll 
ensure a smooth migration 
path to our premier Series 200 
systems which feature the same 
SourceGate user interface. 


Better write or phone for details 
on our new Lite. Ready for use 
with IBM PC family and UNIX 
based computers, it really is just 
what you've been looking for. 


HUNTSVILLE MICROSYSTEMS, INC. 
3322 South Memorial Parkway 
Huntsville, AL 35801 USA. 

Tel: (205) 881-6005 

Fax: (205) 882-6701 


IBM is reg. T.M., International Business Machines, Inc. 
UNIX is reg. T.M., Bell Laboratories, Inc 


| Supporting 683xx and 68HC16 families. Call for specific microprocessors. 


CIRCLE NO. 4 


COMPUTER Technology 


rs: and Design 


DESIGN Directions 


CONTINUED FROM PAGE 3 


Tom Clark on: 
FPGA design 


Logic designers 
using field pro- 
grammable logic 
devices have two 
basic choices when | 
it comes to design 
methodology — | 
structural and be- 
HAVIOFALE ce, woth oetac: 31 


| Look for 


OEM 


INTEGRATION 
next month, 
featuring 
secondary 
and 
mezzanine 
buses, 
backplanes 
and 
enclosures. 


TECHNOLOGY & DESIGN REPORTS 


FPGA vendors turn their 
attention to tools 


In the face of stiff competition, FPGA vendors are enhancing 
proprietary tools, enlisting third-party support, adding text- 

based entry methods, and backing standards. 

STi sea eMC ERR IB ose oe sna vore oe senec tees ade? os unns dda spsicdessaexeecoseaies 75 


| GUIs move OSs toward 


object orientation 


Computer graphics, originally meant to display data, is now the 
way users interact with systems. A new generation of operat- 

ing systems with fully integrated GUIs is meeting the demands 

of those who want to work with their systems in a real-world 
environment of objects and actions. 

TOT VVHNCIIIS eer wee katt, <2 Fees oaten: eee Ree ee ea cce,.. MeN 85 


COVER STORY 


32-bit power and tools bring cheer 

to embedded system designers 

Because of their increased compute power, higher integration, 
extensive tool sets, and a desire for the friendliness provided by 
high-level languages, more designers are putting 32-bit micro- 
controllers on their wish lists for next-generation products. 


= EXOT TUE sic 2 Ree dhe aie, hese eee. Wee 91 


EDESIGN STRATEGIES 


| Truck simulator integrates 


off-the-shelf subsystems 


| Adefense contractor saw an opportunity to create its first 


commercial product, the TTI50 Truck Driving Simulator. 
SMT MO NN eres 62 SE ccs hc ote tac Mace asnaed eashdcahndamstwesse 105 


EPRODUCT FOCUS 


STD Bus CPUs focus on solutions 

Unlike VME, which has Motorola supporting it, or Multibus Il, 
which is backed by Intel, STD Bus may suffer from not having 

a major semiconductor manufacturer behind it. But in reality, 

STD has a strong position as a low-cost workhorse bus for 
embedded control. — Jeffrey Child.........:..ccccccessceceesceeeneeees 115 


ECOLUMN 


_ MIXED-SIGNAL DESIGN — Stephan Ohr 


“Design for X:" A new push for manufacturability, testability 
Fe)11.0 fh 731051] 9 nn ee el Oy a a 132 


Page 85 


Page 115 


COMPUTER DESIGN DECEMBER 1992 5 


————=_ Tekironix SSS 


No logic analyzer is, for that matter. 

Because at speeds above 25 MHz, even the best designer 
needs a scope to handle nightmares like race conditions, 
ground bounce, and crosstalk. And not just any scope, but 
one tailored specifically for high-speed digital design. 


At Tektronix, we understand this need all too well. 


As proof, we’ve not only designed and built a great logic 


~~ EVEN THOUGH OUR NEW LoGic 
“HIGH SPEED DIGITAL DESIGN, 


new GPX — 


but also a perfect companion. The TDS 640 digitizing oscilloscope. 


"Tektronix TDs 640 a | 


To get you started, the GPX provides more channels than 
cable TV. Up to 160, for instance, of 80 MHz state analysis, 
and 32 channels of 1 GHz timing or 160 channels of 200 MHz 
transitional timing. ea 

In short, enough to handle the world’s fastest 
microprocessors. And with that 
kind of performance, you can easily track your system at clock 
rates well beyond 50 MHz, which allows you to locate complex 


coding errors quickly and accurately. 


5EW-188546 Copyright © 1992, Tektronix, Inc. 


Enter the TDS 640. 


With a 500 MHz bandwidth and 2 GS/s 

real-time sampling on four channels, 
the TDS displays logic and timing 

errors with absolute accuracy. And 


because it was created with the digital 


designer in mind, the TDS lets you trigger directly on common 


digital circuit 


ANALYZER IS GREAT FOR os: 
IT’S NOT NEARLY ENOUGH. *"""” 


pulses, and 
excessive Clock jitter or skew. Put all that together with the 
power of the GPX and you have a remarkably effective solution. 
Cost effective, too. In fact, the GPX and TDS together sell 
for less than competing scope/logic analyzer combinations. 
And if you buy the pair between now and February 28, 1993, 


we'll take an additional 10% off the retail price. 


Enough, already. 
For more information on the very best high-speed digital design tools available, 


call Tektronix today at 800-426-2200. 


Tektronix 


Test and Measurement 


CIRCLE NO. 5 


TODAY'S 
FAMILY VALUES 
ARE 3 VOLTS. 


No argument— everyone loves a good 3-volt system. 

Atmel got interested in 3-volt components when we saw the pains our 
customers were having with their growing battery needs. Too many batteries 
hurt portability and pocketability. It was time for new devices with new values. 

They’re here. We make the world’s largest collection of low-voltage logic 
and memory devices. We’ll cut your battery count or give added life to the 
ones you keep. 

We’ ve got the world’s only 3-volt Flash and 3-volt 22V10. A bunch of 
3-volt EPROMs, 15 parallel and serial interface EEPROMs (most of which 
operate to 1.8 volts) and two full 3-volt gate array families. That’s seven 
families and more than 50 circuits. 

You know us already. Maybe because of our industry-leading first single- 
voltage Flash, or our serial interface EEPROM’s (the largest family available). 
Or maybe because of the blazing speed of our non-volatile memories, or our 
families of user- and factory-programmable logic devices. 

Now know our low-voltage families. Check out the book. Write, fax or call 
us and we’ll send you our low-voltage catalog. 

And, when the talk turns to family values remember ours are the same as 
yours —3 volts. 


ATMEL CORPORATION Tel. 1-800-292-8635 
2125 O'Nel Drive Tel. (408) 441-0311 


San Jose, CA 95131 rae FAX (408) 436-4200 


CIRCLE NO. 6 


£ 


SROOOOOE 


y 


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RR SR ER RE en RR pc SN EC, i EE ON RNS =o GI Sa a aE A ee 


EWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS 


MIPS forges ahead 


Last month, mips Technologies 
(Mountain View, CA) announced 
the R4400, the latest 64-bit mips 
microprocessor. Designers experi- 
enced with the R4000 won’t have 
to make any changes in hardware 
or software when using the new 
R4400. The only differences are 
cache size, clock rate and a new 
write buffer. This buffer takes the 
output from a graphics loop and 
runs it in parallel with the next 
loop, resulting in a substantial in- 
crease in graphics performance. 

Although the cache size on the 
R4400 is double that of its prede- 
cessor, a 20 percent shrink in pro- 
cess technology has returned that 
real estate, resulting in a die size 
no larger than the R4000. The 
clock rate has been raised to 75 
MHz, with 67 MHz and 50 MHz 
for backward compatibility. Tran- 
sistor count went up by a million 
on the R4400, with the increase 
fundamentally in cache. On-chip 
primary cache has been doubled 
from an 8k/8k instruction/data 
cache to a 16k/16k cache on the 
R4400. The secondary is the same. 
The processor is available in 3.3- 
and 5-V versions. 

How does this new chip fit into 
the emerging RISC PC world? Even 
when Intel’s P5 finally hits the 
streets, the MIPS crowd already 
has the more powerful R4000— 
and the R4400 is an upgrade to 
that. When compared with the 
486, the R4400 offers more perfor- 
mance in the same price range. 


—effrey Child 


Chorus spreads micro- 
kernel-based UNIX 


Chorus Systemes (Paris, France) 
appears to be the most agreeable 
operating system company 
around. Last year Chorus con- 
cluded arrangements with IsI Soft- 
ware Components Group (Santa 
Clara, CA) to link its microkernel- 
based UNIx-compatible distributed 
operating system with ISI’s psOs+ 
realtime kernel. Recently, Chorus 
moved to support Sco’s (Santa 
Cruz, CA) PC-based UNIX. 

Now Chorus has entered into an 
agreement with UNIx System Labs 
(Summit, NJ), the guardian of UNIX 
System V Release 4 (SVR4). Its 
aim is to let Chorus microkernel 


technology evolve in step with 
SVR4, so that large system and re- 
altime system vendors have an 
SVR4-compatible microkernel mi- 
gration path for future develop- 
ment. Topping this off is an agree- 
ment with Tandem Computers 
(Cupertino, CA) to develop micro- 
kernel-based SVR4 fault-tolerant 
operating system technology. Ac- 
cording to Chorus, such technol- 
ogy will be scalable from embed- 
ded realtime systems to large 
mainframe computers. 

—Tom Williams 


Benchmarks proposed 
for fuzzy logic 


A suite of benchmark programs de- 
veloped by Togai Infralogic (Irvine, 
CA) has been proposed as a means 
of measuring the performance of 
processors executing fuzzy logic in- 
ference code. The benchmarks are 
three fuzzy rule bases at different 
levels of complexity: simple (with 
seven rules, each having two input 
variables and one output vari- 
able); medium (14 rules of three in- 
puts and two outputs); and com- 
plex (25 rules of seven inputs and 
three outputs). 

Togai has released results of 
tests run on four processors, the 
Motorola 68HC11, Hitachi H8/300 
and -500 and Intel 8051 (which 
showed the highest performance). 
There will no doubt be many ques- 
tions from vendors as to how the 
code was produced, what inference 
methods were used and whether 
code was optimized. When this in- 
formation is available, vendors 
may be able to use these bench- 
marks as a starting point for a 
common suite that will help de- 
signers pick price-performance 
points for fuzzy-based designs. 

—Tom Williams 


ViaLink helps QuickLogic 
cut FPGA prices 


QuickLogic’s (Santa Clara, CA) 
ViaLink process technology has 
been moved from codeveloper VLSI 
Technology’s (San Jose, CA) pilot 
line to its high-volume production 
facility in San Antonio, Tx, produc- 
ing improved yield and lower wa- 
fer cost that’s enabled the FPGA 
vendor to reduce pasic 1 prices by 
up to 33 percent. “As we move to 
high-volume production of our 


10 DECEMBER 1992 COMPUTER DESIGN 


products, we are pleased to be 
able to pass the cost savings on to 
our customers,” said David A. 
Laws, QuickLogic’s president. 

vis! Technology recently an- 
nounced that it will use the Via- 
Link element as the basis for what 
it calls programmable Functional 
System Blocks (pFsBs), cells that 
provide field-programmable capa- 
bilities embedded in asic devices. 
These pFsBs will be used to de- 
velop embedded memory elements 
(vROMs or ViaLink ROMs), embed- 
ded logic elements and custom 
ViaLink products. Asics built with 
pFsBs will offer visual and electri- 
cal security. 

Don Ciffone, vice-president and 
general manager of VLSI’s product 
divisions, says, “With the ability to 
include field-programmable struc- 
tures directly on ASIC and ASSP 
chips, customers now have unprec- 
edented flexibility in the design of 
secure, high-performance systems 
that can be highly differentiated 
from those of their competitors.” 

—Barbara Tuck 


Vitesse prices GaAs 
ASICs to beat BiCMOS 


With 1,500, 7,000 and 13,000 
gates, the new 0.6-l1m VIPER GaAs 
gate arrays from Vitesse Semicon- 
ductor (Camarillo, CA) are sized for 
the majority of designs today and 
offer two to three times the perfor- 
mance of competing BiCMOS arrays 
at comparable cost, claims the com- 
pany. “With the introduction of our 
VIPER arrays, cost is no longer the 
issue when comparing GaAs with 
competing BiCMOS technologies,” 
says Lou Tomasetta, Vitesse presi- 
dent and CEO. “Our H-GaAs tech- 
nology is more mature than most 
BICMOS processes currently offered. 
The real issues today are reducing 
design time through simplified sys- 
tem architectures and increased 
performance margin.” 

Housed in plastic and aimed at 
system designs running at 50 
MHz and above, the VIPER gate ar- 
rays deliver shorter gate delays, 
lower power requirements and 
better design margins than Bic- 
mos. According to Vitesse, a two-in- 
put NOR gate has a typical un- 


| loaded delay of 60 ps, while 


dissipating only 0.18 mW. “For ap- 
plications above 75 MHz, there 


Continued on page 12 


: & 
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Sharing one straw has never 
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True sharing means neither side has to 
wait until the bus is free to access 
data—they each have individual access 
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This translates into increased 
throughput for wider buses using 
fewer parts! 
IDT also offers innovative dual- 
port packaging solutions, including 
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} Share a Sweet Deal 
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ASK FOR KIT CODE 7061 Technology, Inc. 
CIRCLE NO. 7 


EWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS 


Continued from page 10 


are no other Asic technologies that 
can compete with the price-perfor- 
mance of VIPER,” boasts Bob Nunn, 
vice-president and general man- 
ager of ASIC products at Vitesse. 
—Barbara Tuck 


A kinder, gentler EDIF? 


The Electronic Design Interchange 
Format (EDIF) committee recently 
unveiled version 2.9.0 of the 
beleaguered EDIF standard, in 
hopes that the updated release 
will rectify the inadequacies of pre- 
vious versions. For the past four 
years, the former release, EDIF 
2.0.0, has been the primary means 
of exchanging data among CAD, 
CAE and test tools, but ambiguities 
in the standard’s syntax have re- 
sulted in incompatibility among so- 
called “epiF-standard” tools. 
“Release 2.9.0 is the result of 
years of engineering staff hours 
and millions of dollars,” says Rich 
Goldman, engineering manager of 
the semiconductor vendor program 
at Synopsys (Mountain View, CA) 
and chair of the EDIF technical com- 
mittee. “We’ve gone to great 
lengths to clarify the EDIF syntax 
to make life easier for the EDIF 
reader. This is where the majority 
of the problems existed in version 
2:0:0.” —Mike Donlin 


Modeling information 
comes online 


Electronic transfer of component 
modeling information may yet be- 
come a reality, thanks to a distrib- 
ution agreement between start-up 
ViewPoint Information Systems 
(Waltham, MA) and Mentor 
Graphics (Wilsonville, or). The 
new company’s offering is different 
from other component information 
products because its data is ma- 
chine-readable. Users can extract 
symbols and attribute information 
for schematic, simulation and lay- 
out programs. ViewPoint has also 
signed deals with Hitachi 
(Brisbane, CA), Intel (Hillsboro, or) 
and National Semiconductor 
(Santa Clara, CA); these agree- 
ments should give the company 
component data faster than other 
vendors who rely on databook in- 
formation. 

The alliances will come as wel- 


come news to EDA users, who’ve 
been demanding vendor-indepen- 
dent component information sys- 
tems that can work with EDA soft- 
ware. Some industry analysts cite 
this lack of timely component data 
as a stumbling block to concurrent 
engineering strategies. 

—Mike Donlin 


PCI gets expansion 
connector 


The pci (Peripheral Component In- 
terconnect) definition developed by 
Intel (Santa Clara, CA) will soon 
get an expansion connector specifi- 
cation, according to the pci Special 
Interest Group Steering Com- 
mittee. Introduced in June, PCI 
was defined as a high-performance 
local bus to supplement existing 
bus architectures. The definition 
only provided for an electrical spec- 
ification, with the belief that pc 
makers would be soldering such 
high-performance peripheral chips 
as graphics and communications 
directly on a motherboard using 
the Pcl specification for electrical 
interconnection. 

The proposed connector uses a 
Micro Channel-style edge-card con- 
nection providing 32- and 64-bit in- 
terconnection. The configuration 
was selected to keep cost down 
while providing a high-reliability, 
high-density connection. The ap- 
proach will let pcI boards be used 
in BISA, ISA and Micro Channel sys- 
tems. 

PCI’s acceptance will be further 
enhanced by a Pc! interface chip in- 
troduced by Intel (Folsom, cA) late 
last month. Compatible with stan- 
dard vo buses such as ISA, EISA 
and MCA, as well as the new 
PCMCIA standard, PCI will offer com- 
mercial and industrial users a 
new high-speed conduit to Pc- 
based processors. 

—Warren Andrews 


Standards set for 
memory interface 


While some vendors pursue PCI 
and others follow PcCMCIA, a group 
within the IEEE Computer Society 
is dealing with advances in tech- 
nology that have made it possible 
for traditional storage elements 
such as disk drives to be reduced 
in size so they can be directly 
soldered to Pc boards. 


The Computer Society’s P1285 
is a standards activity meant to de- 
fine a new IEEE standard interface 
to handle just such high-latency, 
non-volatile memory elements. 
The interface will be used with ei- 
ther a single memory element or 
with many coordinated memory el- 
ements. Issues of concurrency, 
latency, bandwidth, extensibility, 
negotiation, and partitioning are 
among those to be addressed. 

—Warren Andrews 


486 rivalry continues 
unabated 


Intel (Santa Clara, cA) and Cyrix 
(Richardson, Tx) are shooting it 
out on the 486 frontier. In a 
November announcement, Cyrix 
unveiled a 50-MHz chip for desk- 
tops with write-back caching and 
burst writes (with a separate 
math coprocessor). Both compa- 
nies have announced notebook ver- 
sions of the chip. 

The Intel chip’s key features are 
3.3-V operation, on-chip integra- 
tion of a 32-bit memory controller, 
an ISA bus controller, and the 8- 
kbyte cache and math coprocessor 
that are integral to the 486DX. 
The processor can interface to 5-V 
peripherals without translation 
logic. The lower voltage means 
that a 486SL actually consumes 
less power than a 5-V 386SL, 
while providing more than twice 
the performance. 

At the high end is Cyrix’s clock- 
doubling cx486S2/50. The com- 
pany’s cx486SLC/e is an enhanced 
version of its earlier 16-bit chip. 
There are versions running at 5 V 
and 3.3 V, although the low-volt- 
age version requires external 
translators in dual-voltage de- 
signs. The cx486SLC/e system 
management mode lowers power 
consumption by 25 percent, com- 
pared to Cyrix’s earlier version. 
Chips are sampling at 25 and 33 
MHz, although 3.3-V operation is 
only available at 25 MHz. 

Intel’s 486 for notebooks, the 
i486SL, is shipping in a 25-MHz 
version. A 33-MHz chip is slated 
for the first quarter of 1993. 

—Don Tuite 


12 DECEMBER 1992 COMPUTER DESIGN 


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CIRCLE NO. 8 


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CIRCLE NO. 9 


: power of embedd 


FORCE COMPUTERS Inc. 3165 Winchester Blvd., Campbell, CA 95008-6557. Prof.-Messerschmitt-Str. |, W-8014 Neubiberg/Manchen. All brands or products are trademarks of their respective holders, © 1992 FORCE COMPUTERS Inc. 


CIRCLE NO. 10 


This is one of those times when you 
just have to seize the day. Because 
opportunities like this are rare indeed. 
You see, FORCE is the only 
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Choose from a range of systems, for a 
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So we're the only ones who can 
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We also have a 
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And our SPARC products pro- 
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So if you want a better grasp of 
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brochure. 800-237-8863, ext. 5. Or in 
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Because there's no SPARC 
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AMxXand InSight cooperate with such 
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With InSight, a single keystroke will 
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AMxX is a trademark of KADAK Products Ltd. All trademarked names are the property of their respective owners 


CIRCLE NO. 11 


80386SX / 80386DX / 80486SX / 80486DX 
INDUSTRIAL SINGLE BOARD COMPUTER 


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HOP486 

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Tel: 416 564-4833 » Fax:416 564-4768 


CIRCLE NO. 12 


18 DECEMBER 1992 COMPUTER DESIGN 


COMPUTER Jechnology 


and Design 
Directions 


~ EDITOR-IN-CHIEF/ASSOCIATE PUBLISHER PUBLISHER 
John C. Miklosz, Ph.D., (508) 392-2114 


SENIOR EDITORS 
Warren Andrews, Computers & Subsystems 
(508) 283-2102 
Barbara Tuck, ASICs & ASIC Design Tools 
(516) 473-1661 
Michael G. Donlin, CAE/CAD Tools 
(508) 392-2123 
Tom Williams, Software & Development Tools 
(408) 335-5514 
Don Tuite, integrated Circuits 
(415) 365-5656 
Jeffrey Child, New Product Developments 
(508) 392-2126 


CONTRIBUTING EDITOR 
Stephan Ohr, Analog & Mixed-Signal 
(908) 232-1380 


OEM INTEGRATION 
Senior Editors 
John Mayer, Technology & Product News 
(617) 484-5804 
Frank Caruthers, Special Reports 
(215) 993-9595 


MANAGING EDITOR: 
Arlyn S. Powell, Jr. 


CHIEF COPY EDITOR: 
Annette M. Staron-Wilson 


COPY EDITOR: 
Kym Wilson Gilhooly 


PRESENTATION MANAGER: 
Richard Sarno 


EDITORIAL ASSISTANT: 
Claire Ellis 


ART DIRECTOR: Jan Horner 
ILLUSTRATOR: Meg Benner 


AD TRAFFIC MANAGER: 
Kelly Rice, (508) 392-2198 


CIRCULATION DIRECTOR: 


Robert P. Dromgoole, (918) 832-9213 


CIRCULATION MANAGER: 
Paul Westervelt, (918) 832-9287 


PUBLISHER 
David L. Allen, (508) 392-2111 


ASSOCIATE PUBLISHER/ 
NATIONAL SALES MANAGER: 
Tim L. Tobeck, (508) 392-2116 


nnWell 


PUBLISHING COMPANY 


Advanced Technology Group 
Dr. Morris R. Levitt, Senior Vice-President 
Leslie P. Cypret, Vice-President, Administration 
One Technology Park Drive 
P.O. Box 990, Westford, MA 01886 
Tel: (508) 692-0700 J Fax: (508) 692-0525 


Postmaster: Send change of address form 3579 
to COMPUTER DESIGN Circulation Department, 
Box 3466, Tulsa, OK 74101 


ATTENTION RETAILERS: To carry Computer Design 
in your store, contact International Periodical Distributors 
at 1-800-999-1170, ext. 447 (dealer calls only) 


VBPA ABP 


The DK516C-16 Winchester is another 
legend in a distinguished tradition of 
Hitachi mass storage products. Hitachi 
believes that product development starts 
with the pursuit of maximum reliability. 
Thats why all of the DK516s key compo- 
nents are designed, built, and tested in- 
house by Hitachi. 


Legendary Performance 

Hitachi backs up this reliability with 
equally-impressive performance. The 
DK516C-16s SCSI interface provides a 
maximum data transfer rate of 5.0 Mbyte/ 
sec (synchronous), with a 256-Kbyte data 
buffer and read look-ahead cache. Average 
seek time is a quick 13.5 ms. 


Authorized Distributors 
CONSAN STORAGE SOLUTIONS 
1800. 229-DISC IA, IL, IN, KS, KY, M 

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SC, TN, VA, WV 


S, NC, SC, TN 


LAW-CYPRESS DISTRIBUTING co. 
1-800-310-6220 AK, CA, HI, OR, V 


For ESDI applications, choose the 
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vides a 14 ms average seek time and a 
2.75 Mbyte/sec data transfer rate. 


From a Legendary 

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Both DK516 drives are brought to you 
by Hitachi, a company renowned for 
mass storage reliability and innovation. 
According to a recent independent end- 
user site survey by Reliability Ratings, 
Hitachi drives had the highest Field 
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GENTRY Sree deena ENG. R SQUARED DISTRIBUTING 
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And to back our reliability, we offer 
one of the longest warranties in the 
industry. The legend continues. For 
more information on the DK516, or 
our new 3.7-Gbyte 5.25" or 1.4-Gbyte 
3.5" drives, call 1-800-HITACHI. 


Hitachi America, Ltd. 

Computer Division 

Peripheral Sales & Marketing, MS:500 
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Brisbane, CA 94005-1835 


HITACHI 


Our Standards Set Standards 


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Survey was conducted independently by Reliability Ratings, Needham, MA 02191. The data is from a publicly available report. Reliability Ratings is not affiliated with Hitachi, Ltd., or its subsidiaries, 


and does not endorse its products. 


Call Hitachi for a free copy of the survey. 


CIRCLE NO. 13 


Do what most everyone 
else does. 

Control your next 
embedded system with a micro- 
processor from Motorola’s 
32-bit 68000 family. 

Whether your system 
calls for high performance, low 
cost, functional integration 
or a combination of all three, 


we've got chips that'll meet 
your needs. 

If cost is your first con- 
cern, take a look at our industry 
standard 68ECOO0 micro- 
processor. It delivers 32-bit 
performance for $2 and change. 

Which makes it perfect 
for everything from low-end 


printers to consumer electronics. 


Or if you're in the “speed 
is everything” camp, consider 
our 68EC040. A streamlined 
screamer delivering 29 MIPS 
of sustained performance, 
itll run the pants off RISC 
controllers in high-end appli- 
cations. At a lower overall 
system cost. 

Or maybe you need 


CONTROL 
CLUDING 
COsfis. 


special functionality. Like 
built-in multiprotocol com- 
munications, direct memory 
access, or sophisticated 
timers. Our 68300 line of 
integrated processors comes 
fine-tuned for a wide variety 
of applications, from telecom- 
munications to hand-held 
computers. 


And because they're 
integrated, they take up very 
little space. 

A quick glance across the 
page will show you there are 
many more 32-bit solutions 
where those came from. 

Namely, from Motorola. 
The company that controls 
more 32-bit embedded sys- 


CIRCLE NO. 15 


Motorola and the ® are registered trademarks of Motorola, Inc. © 1992 Motorola, Inc. All rights reserved. 


tems than the rest of the world 
combined. 

For a free copy of our 
68000 Family Brochure, call 
1-800-845-MOTO. 

And get everything under 
control. 


(AA) MOTOROLA 


BEDITORIAL 


“A technical conference 
in these times has to 
offer enough...to make 
your sacrifice in time 
and money worthwhile. 
We think we’ve come 
up with an approach 
that does that.” 


John Miklosz 
Associate Publisher/ 
Editor-in-Chief 


L 


Computer Design takes 
over A & M-S Design 
Conference 


W ell, the second annual Analog & Mixed-Signal Design Con- 
ference is behind us and, with so many of us away from the West- 
ford office on the day of our Halloween party, we again failed to 
walk away with any prizes. This was the second year in a row 
that we came up empty-handed and, determined not to let that 
happen again, we entered into an agreement with Miller 
Freeman, the original sponsors of the A & M-S Design Conference, 
to take over full responsibility for future A & M-S conferences. 
Our first move was to change the scheduled date for next year’s 
conference from the last week in October to the last week in 
January, 1994! 

But we’re doing more than just changing the date—we’re re- 
vamping the entire format of the conference. As A & M-S was origi- 
nally conceived, it was the conventional conference/exhibition, 
with technical presentations and sessions running during the 
same hours that the exhibit floor was open. We think we’ve come 
up with a better way to stage conferences as tightly focused as A 
& M-S. We’re testing the approach with RISC ’93 in March (see 
pages 38 and 39) and Fuzzy Logic ’93 in July. The basic idea is to 
eliminate the traditional exhibits and place the conference at- 
tendees, as well as the presenters, in a close-up, face-to-face, “total 
immersion” environment that will expose them to the relevant 
technologies, tools and applications throughout the entire three 
days of the conference, morning till night. 

With this new format, there’ll be half-day tutorials, one-hour lec- 
tures, multipaper application-oriented sessions, two-hour after- 
noon demonstration workshops (providing the opportunity to get 
some hands-on experience with various design and development 
tools), and evening rap sessions (with beer and snacks provided). 
What’s more, we’re throwing lunch into the package on each day 
of the conference, with each lunch session featuring a distin- 
guished speaker—a design guru, if you will. 

These are tough times for everyone—for designers and design 
managers at OEMs and system houses, and for vendors of ICs, 
ASICs and design and development tools. Money is tight and, prob- 
ably more important, time is tight, with many designers, design 
managers, product managers, and marketers doing one-and-a-half 
jobs. A technical conference in these times has to offer enough— 
and enough value—to make your sacrifice in time and money 
worthwhile. We think we’ve come up with an approach that does 
that. What do you think? 


22 DECEMBER 1992 COMPUTER DESIGN 


The Goal: 


Design the world’s only multi- 
frequency Radar Target Gener- 
ator System able to simulate 
hostile threats on the military’s 
diverse radar systems. 


The Problem: 

To get the needed horsepower, 
sixteen 68040 CPU boards were 
required. However, with this 
many boards, VMEbus band- 
width limits would severely 
degrade system performance 
making the project unfeasible. 


The Solution: 

Synergy’s V420 dual 68040 SBC. 
After evaluating several pro- 
ducts, KOR Electronics selected 
eight V420s which could deliver 
320 MIPS without VMEbus 
bandwidth degradation. 


“Not only did 
we meet our project 
performance goals, 

we were able to 


reduce our costs 
by 40%.” 


“ Synergy’s 
dual ‘040 
outperformed all 
other boards 
I've evaluated in 
the last five 


years,” 


—KOR Electronics 
Garden Grove, CA 


Unexpected Benefits: 
Synergy’s dual ’040 solution cut 
KOR’s hardware requirements 
by 50% while vastly increasing 
system reliability. These un- 
expected benefits reduced sys- 
tem costs by 40%. 

In Synergy, KOR also found 
a design partner with strong 
integration expertise and de- 
pendable customer support. 


“I recommend you call 
Synergy today.” 


Next time you need high 
performance SBCs, do as KOR 
Electronics did. Call Synergy 
Microsystems. You'll be as 
satisfied as they are. 


microsystems 


High performance SBCs for demanding applications. 
SYNERGY MICROSYSTEMS, Inc. 179 Calle Magdalena, Encinitas, CA 92024, 619-753-2191, Fax 619-753-0903 


CIRCLE NO. 16 


Complete RealTime 


Operating System...$995! 


Don't be fooled by higher 
priced realtime systems! 
RTMX comes complete and 
ready to run with all standard 


BSD utilities, C and C++ Compilers, C source 
de debugger, editors, and full 
a 


Syn networking with NFS. 


1003. | Tool Set* 

features include: POSIX realtime 
xo task scheduler, shared physical 

memory, message queues, high resolution 

timers, semaphores, software signals and 

realtime file support. 


RTMX_ systems, 
with X Windows and 
Motif, are $1895. 
Target systems are 
available starting 
at $295. 


*POSIX 1003.2 and 1003.4 are Draft Standards 
CIRCLE NO. 17 


High performance realtime 


For more information: 


RTMX-UniFLEX Inc. 
800 Eastowne Dr., Ste 111 
Chapel Hill, NC 27514 


(919) 493-1451 
Fax: (919) 490-2903 
Email: krl@rtmx-uniflex.com 


second Precision 
er Timing Modules 
+ Event Time Capture 


on/ * Multiple Processor 
Synchronization 


penedic Pulses/interrupts 


Poe “Call today for our 
Cor atey Synchronization Products Catalog 


- BANCOMM. Division of Datum Inc 
6541 Via Del Oro, San Jose, CA 95119 
Tel: (408) 578-4161 Fax: (408) 578-4165 


STDbus 


CIRCLE NO. 18 
24 DECEMBER 1992 COMPUTER DESIGN 


CALENDAR 


December 13 - 16 
1992 IEEE IEDM 


Hilton Hotel, San Francisco, cA. The 1992 

IEEE International Electron Devices Meet- 

ing brings together engineering profession- f 
als from industry, government and aca- 

demia. The meeting features 36 sessions on such topics as 
solid-state technology, integrated circuits and quantum 
electronics. Also offered are several short courses, plenary 
sessions and panel discussions. Contact: Melissa Wider- 
kehr, IEDM, Ste 610, 1545 18th St Nw, Washington, DC 
20036, (202) 986-1137, Fax (202) 986-1139. Circle 366 


January 3 - 6, 1993 

VLSI Design ‘93 

Taj Intercontinental Hotel, Bom- 

bay, India. The Sixth Inter- 

national Conference on VLSI Design, with the theme Chip, 
Board and Systems Design in the ’90s, brings researchers 
and designers to the west coast of India. The four-day 
program consists of paper sessions, posters, tutorials, and 
industrial CAD exhibits, covering such topics as CAE/CAD 
systems, logic synthesis, design for testability, circuit sim- 
ulation, analog devices, and economic issues. Contact: 
Rochit Rajsuman, Dept. of Computer Engineering & 
Science, Case Western Reserve University, Cleveland, OH 
44106, (216) 368-5510, Fax (216) 368-2801. Circle 367 


January 6 - 8 
WEST ‘93 oe 
‘ r : yb AFCEA& 

San Diego Convention Center, San Diego, aly ry 
CA. The AFCEA and U.S. Naval Institute 

Western Conference & Exposition fea- 
tures a technical program directed to military, govern- 
ment and industry professionals in the fields of military 
weapon systems, computers, communications, aero- 
space, and electronics. The conference focuses on mili- 
tary- and space-related issues, joint requirements and 
naval and drug enforcement applications in imaging. 
Also offered are technical panels, development courses, 
career transition seminars, and more than 160 exhibits. 
Contact: Ginny Bracken, J. Spargo & Associates, 4400 
Fair Lakes Ct, Fairfax, VA 22033, (800) 336-4583, Fax 


(703) 818-9177. Circle 368 
February 22 - 25 
EDAC-EUROASIC EDAC-93 


cniT Conference & Exhibi- FU ROASIC-93 


tion Centre, Paris, France. 

EDAC, the European Conference on Design Automation, 
and EUROASIC, the premier European event in ASIC design, 
will be held jointly this year to provide a forum for a 
common discussion on ASIC design and design automation. 
Sponsored by the EDAC Association, the event is expected 
to draw more than 80 exhibitors, and covers such topics 
as design techniques and methodologies, high-level design 
tools, simulation, and testability. Contact: CEP Consultant 
Ltd, 26-28 Albany St, Edinburgh, EH1 3QH, UK, +44 31 
557 2478, Fax +44 31 557 5749. Circle 369 


| 
\ 


' 
it 


» wa 
“our Mother— 


So 
VA 


ge 


«net 
Re 
ady 
Pe, 
r 
SOna/ 
C 
"e 
Ly) 
0, 
7} 
le 
.. 


Look in almost every office 
and you'll find a twisted pair 
_ outlet right on the wall. But look 
| for an efficient IC solution to 
_ make your PC design Ethernet-’ 
ready and it could drive you 
right up the wall. 

Unless you look to AMD. 
Our new PCnet-ISA—a true one-chip Ethernet 
controller—gives you the integrated features 
you need to make your next PC Ethernet-ready. 
So you get a complete 1O0BASE-T design in less 
than five square inches of real estate. 

PCnet-ISA is going to save you more than 
just space. Since your total solution will run you 
less than $25 in volume, PCnet-ISA will shine on 
the bottom line. 

You'll also save design time, because no ad- 
ditional memory is needed. And you'll deliver higher 
performance, because data transfers directly to 
the host memory, instead of through a local buffer. 

The software's ready to go too. Driver support is 
already available for Novell NetWare? Microsoft 


AMD's complete PCnet-ISA solution 
covers less than five square inches. 


LAN Manager, Banyan Vines? Artisoft LANtastic? 
SCO UNIX? and others. 

AMD has over 15 years of experience in net- 
working. PCnet-ISA is yet another in a long line 
of networking IC solutions from AMD for both 
Ethernet and FDDI LANs. Our cooperative part- 
ners include such industry leaders as DEC, HP. 
and SynOptics. So when you're working with any 
of AMD's networking solutions, you'll get the 
engineering support you need just by picking 
up the phone. 

And when you're ready to go to work with 
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Literature Pack 16M. Then plug into a network- 
ing leader called AMD. 


ct 


Advanced Micro Devices 


901 Thompson Place, P.O. Box 3453, Sunnyvale, CA 94088. © 1992 Advanced Micro Devices, Inc 
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BTECHNOLOGY VIEWPOINT 


Tom Clark on: 
FPGA 
design 


arrays (FPGAs) and complex programmable logic 

devices (CPLDs) have two basic choices when it 
comes to design methodology—structural and be- 
havioral. Until recently, the preferred choice among 
most designers was structural design—namely, sche- 
matic capture. But a strong movement is underway 
toward a shift in design methodology. 

Today, many systems designers are moving away 
from schematic design entry and are taking advan- 
tage of the higher level of abstraction offered by 
behavioral design methodologies. This doesn’t mean 
that engineers are phasing out their schematic cap- 
ture products. Rather, it signifies a shift toward a new 
design environment that utilizes hardware descrip- 
tion languages (HDLs) as its core, and alters the role 
of schematic capture to provide less design and more 
documentation. 


i ogic designers using field programmable gate 


Bf New architectures push change 


Pushing this shift in methodology into the spotlight 
is the immense popularity of FPGAs and CPLDs. These 
new device architectures combine the best features of 
ASICs with the best characteristics of PLDs. Initially, 
schematics were the entry vehicle of choice, primarily 
because many of the early adopters of FPGAs were ASIC 
designers. Schematic entry is also inherently a lower- 
level (and so more detailed) representation of a design 
than a behavioral description, and offers better con- 
trol over the silicon. 

In addition, FPGA vendors have realized that design 
at the schematic level effectively locks a designer into 
one supplier’s technology. Anyone who’s changed a 
gate-array vendor in midstream immediately knows 
why—to retarget a schematic-based design to another 
vendor, you have to redo much of your work. With 
FPGAs, the situation is even more severe. Whatever 
one-to-one remapping you might get away with in 
gate-array retargeting is impossible, or at least hope- 
lessly inefficient, for moving between FPGAs. This is 


Thomas R. Clark, president and CEO, Data I/O Corporation, 


Redmond, WA 


because each FPGA vendor’s architecture and granu- 
larity are dramatically different. 


Bf The move to behavioral methods 


Several trends are weaning FPGA and CPLD users from 
schematic capture, and shifting them to behavioral 
methods. The first is the increase in the number of 
device vendors; the second is the increase in device 
density; and the third is the advent of new behavioral 
methodologies capable of handling the complexity 
offered by FPGAs. 

When FPpGas were first made available, there was 
only a single vendor of choice—Xilinx. Later, Actel, 
AT&T and Texas Instruments entered the market. With 
these limited choices, designers weren’t averse to a 
vendor-specific toolset. Today, however, a growing 
number of silicon vendors have FpGa offerings. Add to 
this the growing number of complex PLD solutions, 
many of which offer comparable density and higher 
performance than their FPGA counterparts, and it’s 
obvious you have many choices. 

In June’s Computer Design Technology Viewpoint, 
Cyrus Tsui provided an excellent profile of our indus- 
try, and we agree with him that there’s little chance 
of an industry architectural standard in the near 
future. As a result—and to combat the hype and false 
promises accompanying some device introductions— 
many designers have adopted one or two “pet” archi- 
tectures. This benefits the few vendors who were first 
to market with FrpGas, and is a serious obstacle to those 
who’ve come later. 

The problem with this defensive strategy is that all 


COMPUTER DESIGN DECEMBER 1992 31 


ETECHNOLOGY VIEWPOINT 


FPGAs aren’t created equal. In fact, there are signifi- 
cant differences in how well particular applications 
map to various architectures. Some FPGAs are signif- 
icantly better at certain kinds of circuits than at 
others, and even in a particular circuit class 
(datapaths or state machines, for example), there are 
typically only one or two architectures that best match 
a given, specific circuit. Narrowing down the number 
of candidate architectures may be a perfectly rational 
way to deal with the complexity and economic rigor 
of a market featuring so many choices, but it’s not the 
best way to match silicon to a design and ensure high 
utilization and top performance. 

This abundance of choice is a leading factor in the 
shift to behavioral entry. The higher the level of 
abstraction designers work at, the less they’re tied to 
any particular piece or class of silicon, and the more 
readily the design can be retargeted. Behavioral entry 
lets you migrate designs between different architec- 
tures, letting you choose the one that best fits your 
application. 

Perhaps the most important factor leading to a 
methodology shift is the fact that FPGAs and CPLDs are 
already meeting the density requirements of the ma- 
jority of today’s gate-array designs. At this level 
(around 10,000 gates), design by schematic is still 
practical, but efficiency is questionable. The higher 
level of abstraction offered by behavioral design 
methodologies becomes a major factor in overall de- 
sign efficiency. The use of HDLs for design entry lets 
you describe a design in a device-independent and 
higher-level fashion, with synthesis routines complet- 
ing the tedious and time-consuming work of matching 
appropriate design elements into correct architec- 
tural features. 

The third force in the shift from schematic to be- 
havioral entry is the development of logic synthesis 
for FPGAs. FPGAS present a more difficult technological 
challenge for synthesis than the less constrained ASIC. 
The architectural variations among different vendors’ 
FPGAS are vast in comparison to those evident in gate 
arrays. 


El Device fitters to the fore 


It’s only in the last two years that synthesis has 
become sufficiently practical to work its way into the 
mainstream, but it now offers a viable solution for 
rpacas. At the forefront of this synthesis movement are 
software algorithms called device fitters. Device fit- 
ters, in the same vein as the FPGAs they support, have 
borrowed techniques and algorithms from traditional 
Asic design software, and have melded them with 
generic PLD optimization routines and derivatives. 
A device fitter is a program that synthesizes a 
generic logic description into an implementation that 
is optimal for a particular architecture. It works ina 
fully automatic mode, but also lets you manually 
specify placement, routing criticalities, buffering, and 
other characteristics. The fitter, rather than the de- 
signer, takes on the burden of knowing the low-level 
details of the target silicon intimately enough to 
efficiently implement an application into a circuit. 
Today’s device fitter synthesis capabilities dispel 
many previously held beliefs that prevented FPGA 
behavioral methodology from being widely adopted. 
Many assume, for example, that the best way to run 


32 DECEMBER 1992 COMPUTER DESIGN 


synthesis is on a complete design. This is not true— 
synthesis performs far better if run on a design’s 
submodules. Many also believe that synthesis will 
always improve a circuit’s size or speed. Again, this 
isn’t true. There are classes of circuits upon which 
synthesis nearly always fails, and upon which it 
should never be run. Many think that schematics are 
as good a candidate for synthesis as behavioral de- 
signs. This also isn’t true—schematics contain valu- 
able knowledge about how a circuit should best be 
structured, knowledge that’s often beyond a synthesis 
algorithm’s ability to divine. 

The ideal design solution includes the ability to use 
behavioral entry as well as schematics, applying each 
to the portions of the design for which it’s best suited. 
Making these points clear to the design community— 
educating users through design examples and train- 
ing—is a prerequisite for achieving full acceptance of 
behavioral entry in the mainstream. 


B Applying benchmarks 


Data 1/0, as well as other vendors, have been involved 
in the past year in the PREP benchmarking effort. This 
Programmable Electronic Performance consortium is 
a group of PLD manufacturers and tool vendors whose 
objective is to develop a suite of benchmarks to accu- 
rately measure the functional capacity and speed 
performance of either PLDs or FPGAS. PREP was not 
formed to standardize such items as physical inter- 
faces, pinouts, architectures, or deal with spec sheet 
issues, such as electrical characteristics. The PREP 
solution is an important and useful first step toward 
helping designers understand how the FPGA architec- 
ture announcements they see in the press every 
month translate into gains in their ability to design 
and deliver the products their markets demand. 

Ultimately, we believe benchmarking will move to 
the desktop, where you can decide for yourself which 
devices give the best gate utilization, the best in-sys- 
tem speed, the best economic choice. That’s why we’ve 
spent considerable energy in the past two years de- 
veloping and constantly improving and adding to our 
list of device fitters. Our goal is to see designers armed 
with a universal front end that allows device-indepen- 
dent design, along with a rich back end, powered by 
device fitters, that can intelligently retarget designs 
between the full spectrum of architectures—and that 
lets you benchmark your circuits in any candidate 
device. 

Movement in the CAE market, however, is slower 
than we’ve hoped for. Behavioral entry is important 
and its momentum is building, but it will not totally 
replace schematics. Automatic device fitting has ap- 
peared, but designers will always want additional 
control. As we’ve learned elsewhere, the best revolu- 
tions are those that augment and build upon the past. 


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ETECHNOLOGY DIRECTIONS 


INTEGRATED CIRCUITS 


New clock chips are analgesic 


Don Tuite, Senior Editor 
ynchronizing the edges of a 
Ss distributed clock so that every 
chip in a system is clocked at 
the same instant has been made eas- 
ier with new chips from Vitesse (Ca- 
marillo, CA), TriQuint (Santa Clara, 
CA) and Cypress Semiconductor (San 
Jose, CA). All the chips give you flex- 
ibility in routing clock lines on a cir- 
cuit board. In some cases, prototype 
timings can be trimmed ad hoc using 
the programming inputs to the chips. 
Some of these clock distribution 
chips also offer frequency multipli- 
cation and division. Division lets you 
reduce the frequency of a clock that 
is being sent off the board, reducing 
potential EMI problems; multiplica- 
tion lets you increase it again. Be- 


for run-length headaches 


cause these chips use phase-locked 
loops (PLLs) that feed selected inputs 
back into the loop, they can be oper- 
ated as zero-propagation-delay clock 
| distribution chips. Propagation de- 
lays are 1 ns or less. 


Bl cypress breaks rules 

Despite the similarities between the 
purposes of these chips, there are 
| differences among them—most no- 
tably, between the gallium-arsenide 
(GaAs) devices from Vitesse and 


SEO ERT 


| while providing a larger array of 
timing options than bilevel inputs. 


It’s easier to understand the 


_ differences between the chips by 


thinking of them in terms of the 
voltage-controlled oscillator (Vvco). 
In all these devices, the vco runs at 
a multiple, N, of the clock frequency. 
The higher the vco frequency, the 
better, in terms of the precision with 
which you can control the outputs. 
In the GaAs parts, the oscillator 


_ runs at a speed as high as 840 MHz. 


_ TriQuint and the silicon device from | 


Cypress. Not only did Cypress vio- 
late the “rule” that says you can’t run 
a silicon PLL that fast, but the com- 
pany’s engineers designed trilevel 
| inputs that simplify programming 


FEEDBACK 
CLOCK IN 


SKEW 
CONTROL 0 — 


SKEW 
CONTROL 1 


The basics of skew control 


SKEW 
CONTROL N eee 


OUTN 


tials. 


— 


Clock distribution chips that let you control the relative skew of their various 
outputs consist of two parts. The first part (green) is a phase-locked loop that 
samples one of the outputs via an external link. This locks the output to the input, 
providing essentially zero propagation delay. It also supplies skew-shifting refer- 
ence signals, either from running the pit’s voltage-controlled oscillator at a multiple 
of the input frequency or from tapping selected stages of a ring oscillator running 
at the clock frequency. The second part (purple) is a skew-control block that uses 
the signals from the first part to generate outputs that are multiples or submul- 
tiples of the source clock, or that are shifted in time by controlled phase differen- | 


34 DECEMBER 1992 COMPUTER DESIGN 


It would be difficult for a silicon part 
to run that fast, but Cypress uses a 
trick to produce a precision equiva- 
lent to running a straight oscillator 
at 1,300 MHz. 

You control the outputs of all these 
chips in two ways: by programming 
skew-control input pins, or by select- 
ing which output is fed back to the 
input of the PLL. In these ways you 
are selecting values for N, and for 
edge placement in various channels. 


Bf Flexible output clocks 


TriQuint’s 80-MHz GA1000 has six 
outputs that can be programmed to 
run at one or two times the input 
frequency. This means the output 
frequency can be as high as 160 
MHz. There are two skew-control 
inputs. With all the outputs in 
phase, the maximum skew between 
any two of them is guaranteed to be 
500 ps. Typical values are 250 ps. 
In programming the chip, you se- 
lect a value for N between 4 and 22. 
You also determine where the rising 
and falling edges of the output fall 
with respect to the rising and falling 
edges of the internal vco clock. Be- 
cause the vco frequency must be 
between 320 and 440 MHz, your sys- 
tem clock frequency determines 
what values of N are possible, and 
so what degree of timing precision 
you can achieve. For example, at 66 
MHz, N must be 5 or 6—that is, 330 


_ and 396 MHz are the only values of 


N multiplied by 66 MHz that fall in 
the allowable range. Depending on 


| which value of N you choose, you can 


delay edges in multiples of 2.53 or 
3.03 ns. At an input frequency of 55 


| MHz and a value of 8 for N, you get 


the smallest increment of edge 
placement, at 2.27 ns. 

TriQuint’s 50-MHz GA1110E has 
six outputs that you can shift in 
increments of 2.5 ns. The guaran- 
teed maximum input skew is 500 ps, 
with the typical being 250 ps. All six 


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and Provection CIRCLE NO. 24 


anidard for r Data Ree 


ssnnevte UTIL Stan 


ETECHNOLOGY DIRECTIONS 


INTEGRATED CIRCUITS 


Output 
fed back 


Output phase shift 


QO, Q1, Q4 


Q2 


Q3 


Q5 


QO, Q2, Q3 


Q1 


Q4 


0 
a ie 
t 


The combination of two bilevel inputs and one of six outputs fed back to the phase- 
locked loop produces an array of positive and negative skews and inversions. 


outputs of the GA1110E operate at 
the clock fundamental, but you can 
use the part with TriQuint’s GA1086 
or GA1086E 10-output clock buffers, 
which have nine outputs at the clock 
frequency and one at half the clock 
frequency. Both the 1086 chips have 
very tight output-to-output skew 
variation—250 ps maximum, and 
125 ps typical. The GA1086 specifies 
a propagation delay of 500 ps and 
the E-version specifies twice that. 

Vitesse’s 70-MHz VSL4485 and 
VSL4586 each have eight outputs. 
On two of the 4485’s pins—or on six 
of the 4586’s—you can multiply the 
input clock frequency by 2 or 4, or 
you can leave it at the fundamental. 
As with the TriQuint chip, combin- 
ing two skew-control inputs with a 
choice of which output is fed back to 
the PLL gives a range of phase shifts 
at the various outputs. The actual 
value of the phase shift, relative to 
the output clock frequency, is deter- 
mined by three other inputs that 
Vitesse calls divide inputs. 

Like the TriQuint clock chips, the 
Vitesse chips guarantee 500 ps max- 
imum skew between outputs. Typi- 
cal values aren’t currently specified. 


Because the Vitesse vco operates at | 


frequencies of up to 840 MHz, these 
chips provide more precise skew con- 
trol than the TriQuint parts. The 
smallest possible increment is 1.25 ns. 


E Lots of control 


Superficially, Cypress’s 80-MHz 
CY7B991 (TTL Vo) and CY7B992 
(CMOS VO) resemble the TriQuint and 
Vitesse parts. There are several in- 
teresting differences, however. For 
one thing, the eight outputs of the 
two chips are arranged in pairs, and 
Cypress guarantees skew between 
members of the same pair to be 250 
ps, while claiming that typical val- 
ues are half that. For another, each 
pair of outputs has its own pair of 
skew-control pins, which may be 
pulled high or low or left uncon- 
nected. (An internal voltage divider 
prevents static buildup.) 

There’s an advantage to having a 
larger number of control pins. For 
each output pair, if the input pins 
are open, the output is in phase with 
the clock. Using other input values, 
you can trim the first two output 
pairs in increments of one, two, 
three, or four timing units, and you 
can trim the second two output pairs 
in increments of two, four and six 


36 DECEMBER 1992 COMPUTER DESIGN 


| which you will obtain your tap. In the 


| skew control, is determined by the 


timing units. The third pair can also 
be set for one-half or one-quarter of 
the applied clock frequency, and the 
fourth pair can be set to one-half the 
applied frequency or to the inverse 
of the applied clock. 

Because of this simple control 
method, you can design a board us- 
ing 991/2 chips to distribute clocks 
without paying a great deal of atten- 
tion to trace lengths. Then you can 
use DIP switches on the skew-control 
inputs of the chips to trim edge ar- 
rival times on your prototype board 
while you observe edge placement 
on a scope. On production boards, 
you simply replace the switches 


| with jumpers. 


Lacking the raw speed capabilities 
of GaAs, Cypress implemented the 
VCO in its PLL as a ring oscillator. This 
device uses a cascade of gain stages 


| to achieve the 180° of feedback an 
oscillator needs in order to work. 


Each stage introduces a constant in- 
crement of phase delay, and the sig- 
nal tapped off any stage is delayed or 
advanced relative to a reference by 
an incremental amount. Instead of 
selecting a value, N, by which the 
vco frequency will be divided, you 
select a number of delay stages, after 


Cypress parts the values are 16, 26 
or 44. The precision, or degree of 


clock period divided by the number 
of stages. The smallest increment of 
stage delay is 700 ps. 

TriQuint and Vitesse unequivo- 
cally specify their output rise times: 
1.5 ns (max) for 0.8 to 2 V. (For the 
10-output clock distribution chips, 
it’s 1.4 ns.) According to the manu- 


| facturers, these values are essential 


for Intel’s Pentium P5 or 586 proc- 
essor. Cypress’s spec sheet cites a 
rather lackluster 3 ns for the TTL 1/0 
part and 5 ns for the CMOs Vo part. 
According to the company, however, 
the parts actually slew at about 1 


ns/V. Bi 
For more information about the technol- 

ogies, products or companies mentioned in 

this article, call or circle the appropriate 
number on the Reader Inquiry Card. 

Cypress Semiconductor 

(408) 943-2902 .. Circle 201 
TriQuint Semiconductor 

(408) 982-0900 .. ares .... Circle 202 
Vitesse Semiconductor 

(805) 388-7455 . Saat _.. Circle 203 


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MARCH 16-18, 1993 


9S 


HYATT REGENCY SAN FRANCISCO AIRPORT 
BURLINGAME, CALIFORNIA 


WHAT IS RISC ‘93: asc 93 is the premier annual gathering of hardware designers and software devel- 
opers involved with RISC system architectures; RISC processors, ASIC cores and peripheral ICs; RISC programming and 
debugging; and the design of RISC-based systems for general-purpose computing, embedded and realtime applications. 


THE ATTENDEES: asc 93 is a downto-earth conference aimed at both hardware and software engi- 
neers and engineering managers responsible for the design and development of products based on RISC processors. 
Specifically, RISC ‘93 is targeted at individuals with a solid background in electronic/computer system design and develop- 
ment (both hardware and software), as well as applications programming, who are looking for the most up-to-date infor- 
mation on the design of RISC-based computers, the design of embedded and realtime RISC systems, programming RISC- 
based systems, designing ASICs with RISC cores, and specifying and integrating RISC development tools into the overall 
product development environment. 


THE FORMAT: TOTAL IMMERSION 

RISC ‘93 has been designed as an intensive 3-day program that will place all 
participants in a total immersion environment where they'll have the oppor- 
tunity to attend: 


Half-day tutorials that will help clarify the intricacies of the major RISC 
processor architectures. 


A variety of one-hour lectures that focus on specific aspects of RISC 
architectures, RISC-based hardware design, programming techniques, 
compilers, and development tools. 


Multipaper, application-focused sessions consisting of 20-minute presen- 
tations by system designers and software developers who've already 
implemented RISC designs in applications ranging from workstations, 
graphics, image processing, communications, signal processing and 
embedded control. 


A luncheon on each day of the conference that will be highlighted by 
an address from a recognized authority on RISC architecture or RISC- 
based designs. 


Demonstration workshops where attendees will be able to get hands- 
on exposure and detailed information about the latest RISC processors, 
compilers and development tools offered by leading hardware and soft- 
ware vendors. 


Free-wheeling “rap” sessions, led by RISC experts, on the first two 
evenings of the conference. Conference participants will have the 
chance to explore and exchange ideas about any aspect of RISC and 
RISC-based system design in an informal atmosphere of shirt sleeves, 
beer and pizza. 


MORNING 


LUNCHEON/SPEAKERS 


AFTERNOON 


DEMONSTRATION 
WORKSHOPS 


RAP SESSIONS 


LED BY RISC 
EXPERTS 


RISC ‘93 Conference is sponsored by COMPUTER DESIGN # One Technology Park Drive, Westford, MA 01886 
TEL: 508-392-2124 ® 800-223-4259 = FAX: 508-692-7780 = Contact: Patti Kenney, RISC ‘93 Conference Coordinator 


PARTICIPATION: Suppliers of RISC proces- 


sors, ASICs, peripheral ICs and memory, compilers, and 
development tools, as well as system designers and pro- 
grammers working on RISC-based designs and applications, 
are invited to participate in RISC ‘93 by presenting tutorials, 
lectures, 20-minute application-focused papers or leading 
one of several evening “rap” sessions. A variety of topics 
that would be of interest to attendees is suggested in the 
Call for Papers for RISC ‘93. All presenters receive free admis- 
sion of all tutorials, lectures, applications sessions, lun- 
cheons, rap sessions and a copy of the proceedings. 


Suppliers of RISC hardware/software or development tools 
may also participate in RISC ‘93 by sponsoring a demonstra- 
tion workshop. These workshops will be two hours in 
length and will be the last formal sessions of the day. 
They're intended to provide attendees with an intimate, 
hands-on exposure to a supplier's product or service. The 
cost of sponsoring these sessions is $1500 for one two-hour 
workshop, $2700 for two workshops on successive days 
and $3500 for a workshop on each of the three days of the 
conference. One complimentary admission to RISC ‘93 for 
each workshop sponsored is included in the fee. 


COMPUTER Technology 


1993 INTERNATIONAL 
TECHNICAL CONFERENCE SERIES 


RISC ‘93 is open to all system designers and software devel- 
opers and the tuition fee covers admission to any tutorial, 
lecture, application session, demonstration workshop, 
evening rap session, and the three conference luncheons. 


TUITION: 
$495. Early Bird— Register by Dec.3, 1992 
$595. If registered between Dec 4, 1992 - Jan 21, 1993 
$695. After Jan 22, 1993 
(Tuition includes lunch on all three days 


as well as snacks and refreshments during 
the rap sessions.) 


Company group discounts available. 


HOTEL ROOMS: 

The single room rate at the Hyatt Regency is $108. 
Call the hotel directly at 415- 347-1234 

Be sure to tell them that you are attending RISC ‘93. 


YES, 'M INTERESTED ! PLEASE SEND MORE INFORMATION 
q 
L] 1 AM A VENDOR Id like to present a: 
MAIL OR FAX TO: Tutorial (_] One-hour lecture (_] Application session 
Patti Kenney _] | would like to lead a rap session 
RISC ‘93 Conference Coordinator i= . ; : 
COMPUTER DESIGN __| My company would like to discuss sponsoring a workshop — 
One Technology Park Drive Please contact 
P.O. Box 990 
Westford, MA 01886 CJ] 1 AM A POTENTIAL ATTENDEE: 
FAX: 508-692-7780 _| I'm interested in attending, send me more details 
TEL: 508-392-2124 _| I'd also like to lead a rap session 
800-223-4259 |_| 1am particularly interested in sessions on 
NAME TITLE 
COMPANY 
ADDRESS M/S 
CITY STATE ZIP 
PHONE FAX 


CIRCLE NO. 25 


ETECHNOLOGY DIRECTIONS 


INTEGRATED CIRCUITS 


IEDM gets relevant 


Stephan Ohr, Contributing Editor 


his year, the IEEE conference 
organizers of the annual Inter- 


national Electron Devices 
Meeting (IEDM), held this month in 
San Francisco, have added a new 
theme. They’re asking authors to re- 
spond to current economic condi- 
tions, and to assess what the costs of 
volume manufacturing might look 
like for the dramatic devices and 
processes they discuss. Coming from 
well-endowed and protected re- 
search laboratories, however, many 
of the best papers may still have a 
decidedly pie-in-the-sky feel to them. 

One of the most attention-getting 
papers, for example, is a Matsushita 
presentation exploring how laser 
lithography might be used to pro 
duce 256-Mbit DRAMs, de- 
vices that even the au- 
thors acknowledge won't 
appear until 1997 or 1998. 
(At previous IEDMs, we 
should note, the electron- 
ics industry heard the first 
discussions and saw the 
first chip photos of 4-Mbit, 
and, later 16-Mbit DRAM 
architectures. ) 

Two current papers 
from NEC’s Microelectron- 
ics Research Laboratories 
(Kanagawa, Japan), in 
fact, describe a capacitor 
structure that the au- 
thors, Hamada and 
Watanabe, suggest may be 
useful for 256-Mbit DRAMs. 
“This chip will be so ad- 
vanced,” says the promo- 
tional material for the con- 
ference, “it will be able to 
store 16 photograph-qual- 


rays, the authors believe, may be 
prohibitively expensive. An 1BM/To- 
shiba/Siemens consortium, for ex- 
ample, has already committed to X- 
ray lithography to manufacture 
64-Mbit DRAMs with 0.35-um fea- 
tures, with the companies’ invest- 
ment expected to exceed $600 mil- 
lion by 1995. The investment in 
0.25-um, 256-Mbit DRAM manufac- 
turing, is expected to exceed $1 bil- 
lion by 1999. The Matsushita re- 
searchers feel that excimer laser 
operating in the frequency range of 
visible light are a much cheaper ap- 
proach. 

The excimer laser tested by 
Matsushita relies on krypton-fluorine 
and argon-fluorine, as well as a high- 


Researchers at Matsushita Industrial Electric Company have 

used excimer laser lithography to produce 0.25-\.m isolation pat- 
terns, the geometry required for 256-Mbit DRAMs. As is the case 
with many IEDM presentations, it remains unclear whether the 
Matsushita researchers have hit upon a practical manufacturing 
method or a laboratory curiosity. 


photoresist layer? Or should the 
photoresist layer be scored directly 
by the swath of the laser beam? If 
the latter is the case, then it will take 
many minutes to score each chip. The 
process may be cheap, but it will be 
very time-consuming, and the ex- 
cimer laser process may turn out to 
be as practical for high-volume man- 
ufacturing as E-beam writing 
proved to be. 


Bf Frank discussion needed 


Of the 143 IEDM papers from com- 
mercial companies, IBM had the most 
accepted (15), followed by AT&T, Mo- 
torola and Japan’s NEC (10 each). 
Universities contributed 72 papers, 
while eight came from government 
agencies. But it remains 
to be seen whether these 
papers offer practical 
manufacturing tips. “IEDM 
is traditionally seen as a 
showcase for new technolo- 
gies leading to products 
that will hit the market 
three to five years down 
the road,” says Hans Stork, 
manager of exploratory 
technology at IBM’s T. J. 
Watson Research Center 
(Yorktown Heights, Ny), 
“but IEDM 1992 will also 
feature some frank discus- 
sion about the direction of 
the industry and the re- 
search work driving it for- 
ward.” 

An evening panel dis- 
cussion led by Lew Terman 
of IBM, for example, will ex- 
amine the impact of slow 
growth and increased costs 


ity images, or an entire en- 
cyclopedia of text.” 

The chip will have a feature size 
of 0.25 um, say researchers Endo, 
Hashimoto and Yamashita, all of 
Matsushita Industrial Electric 
Company (Osaka, Japan), in their 
abstract. Current semiconductor 
manufacturing relies on photolitho- 
graphy, but as the feature size of the 
devices decreases, the dimensions of 
the photomask—and even the wave- 
length of the light used to expose the 
photoresist—must also decrease. 

The use of electron beams or X- 


resolution stepping method, chemi- 
cally amplified positive photoresists 
and a carefully controlled depth of 
focus for the laser. While the re- 
searchers have successfully pro- 
duced 0.25-um and even 0.20-t1m di- 
mensions using this process, it’s 
unclear how difficult it will be to 
adapt the process to high-volume 
memory manufacturing. For exam- 
ple, should the laser light be pro- 
jected through a photomask that 
mass produces the trenching in the 


40 DECEMBER 1992 COMPUTER DESIGN 


on technology research. 
Does it pay to be a leading- 
edge manufacturer? Or does it make 
more sense to focus on application- 
specific products with immediate 
sales potential? 

This is a serious issue for the com- 
puter giant. William Bowles, direc- 
tor of IBM’s OEM products marketing 
group and keynote speaker at Com- 


| puter Design’s SysComp forum last 


February, used a Silicon Valley 
analog conference last month to an- 
nounce the company’s entrance into 
the market for mixed-signal Asics. 


Graphic memory that 
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CIRCLE NO. 26 


Te echolo® ey 
that wor” 


y you: 


) 4 


& 


ETECHNOLOGY DIRECTIONS 


INTEGRATED CIRCUITS 


LDMOS device cross-section 


TiSi, 


P BODY 


N+ BURIED LAYER 


P BURIED 
LAYER 


P BURIED 


P SUBSTRATE LAYER 


Motorola, in one of the most practical papers at IEDM, presents a way to integrate /at- 
eral double-diffused MOS on a BiCMOS substrate with 0.5-\um devices and maximum 
frequency (fts) on the order of 26 GHz. These smart power structures will contribute 
toward the portable RF transmitters of the near future. 


of these announcements, Lew Ter- 
man’s panel may be more dramatic 
than a polite conversation among 


The same week, the company told 
financial analysts it will close semi- 
conductor manufacturing plants 


“The concern about profitable 
manufacturing is also evident in a 
number of papers that describe cost- 
effective ways to produce new cir- 
cuits,” insists IBM’s Stork, who heads 
the publicity effort for IEDM 1992. He 
cites as evidence an invited paper by 
Dr. Yoshio Nishi of Hewlett-Pack- 
ard (Palo Alto, CA), a man who ear- 
lier led Toshiba’s 1-Mbit DRAM devel- 
opment effort. The paper questions 
the conventional view that memory 
circuits are the best proving ground 


| for advanced fabrication techniques 


for microprocessors and other dig- 
ital circuits. 

If anything, Nishi’s paper, “ULSI 
technology toward the next century: 
driven by DRAMs or MPCs?,” forecasts 
a split between the processes used 
to manufacture ultra-large-scale in- 
tegrated (ULSI) circuits. One process 
will be used for memory, the other 
for RISC microprocessors. These 
chips require two fundamentally dif- 


and lay off 40,000 workers. In light | wealthy gentlemen. ferent technology drivers, says Dr. 


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INTEGRATED CIRCUITS 


Nishi. Where memories require so- | plastics) isn’t an oxymoron, and sug- | neurons in the human brain. Pre- 
phistication in front-end fabrication, | gesting applications for such materi- | sented by K. Kotani of Tohoku Uni- 


RISC microprocessors require expert- | als. | versity (Tokyo, Japan), “Neuron-Mos 
ise in back-end packaging tech- | A Tuesday, December 15th lunch- | binary-logic circuits” describes ICs 
niques. It may be too costly to at- | eon session will feature a talk on | that embody real-world “fuzziness” 
tempt both, Nishi warns. virtual reality by Jaron Lanier, chief | by representing transistor inputs as 

’ ; scientist and founder of vPpL Re- | weighted sums of multiple inputs. 
i Thought-provoking sessions search (Foster City, ca). Also, check | The authors claim that these fuzzy- 


The plenary session on Monday, | out a Tuesday evening panel session | logic 1cs reduce the number of tran- 
December 14th, of which Dr. Nishi’s | entitled “the electronics industry | sistors required to implement ma- 
presentation is a part, may be the | andthe new world order: technology, | chine vision, pattern learning, 
most thought-provoking event for | Politics and Industrial Competi- | fault-tolerance, and other ambigu- 
the general engineering community. | tion.” Organized by the Berkeley | ous decision-making systems. 

“semiconductor devices save the | Roundtable on the International There are several sessions, how- 
earth,” by Yukinori Kuwano of | Economy (BRIE), the panel will dis- | ever, that are bound to have more 
Sanyo Electric (Tokyo, Japan), ex- | cuss the impact of international pol- | immediate practical impact. The 
plores the possibilities of increasing | itics (for example, military conver- | two one-day short courses, always 
energy and reducing pollution | sion) and economic competition on | popular with IEDM attendees accord- 
through the proliferation of semicon- | the semiconductor industry. ing to the IEEE, will be held on Sun- 
ductor-based solar cells. In the same In spite of its focus on relevance, | day, December 13th. One course, 
session, Alan Heeger of the Institute | IEDM will still feature its share of | “Interconnect for the ’90s,” focuses 
for Polymers and Organic Solids of | gee-whiz ideas that may indeed rep- | on interconnection issues for on- 
the University of California (Berke- | resent breakthroughs, if somebody | chip, off-chip, module, and PcB sys- 
ley, CA) will give a presentation dem- | can just figure out what to do with | tems. Interconnections are seen as 
onstrating that “conducting poly- | them. One of these gee-whizzes is a | the weak link when it comes to in- 
mers” (or electrically-conductive | paper on transistors that emulate | creasing performance. Presented by 


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BTECHNOLOGY DIRECTIONS 


Brian Bakoglu of IBM, Bob | 
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(Dallas, Tx) and Arjun Saxena of 
Rensselaer Polytechnic Institute | 
(Troy, NY), the course examines the 
impacts of material, thermal effects 
and transmission-line behavior on | 
packaging choices. The other short 


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CIRCLE NO. 32 


44 DECEMBER 1992 COMPUTER DESIGN 


anisms of MOSFETs, including corro- 
sion, electromigration and stress 
voiding effects. 

“Transistor-level reliability” will 
be discussed by Akira Toriumi of 
Toshiba (Tokyo, Japan); “Reliability 
in multi-level interconnects” will be 
presented by Ronald Schutz of Se- 
matech (Austin, Tx), the U.S. chip- 
making consortium; “Reliability in 


| packaging” will be covered by Paul 


Totta of IBM; and Daniel P. Siewiorek 
of Carnegie Mellon University 
(Pittsburg, PA) will be the instructor 
for the section on “fault-tolerant 
computing.” 


| E Bicmos technology 


Because it’s so fashionable among 
designers and manufacturers of 
mixed-signal ASIcs—even those in- 
volved in high-speed digital de- 


| sign—we should look at some of the 


papers in the IEDM session on BiCMOS 
technology. Once again, IEDM ex- 
poses us to the dramatic processes 
and capabilities we can only dream 
about using—combination CMos and 
ECL devices with gate delays of 20 or 
30 ps. D. Harame, E. Crabbe and 
other researchers at IBM (Yorktown 
Heights, Ny) describe a silicon-ger- 
manium (SiGe) epitaxial base that 
produces 18.9-ps gate delays at 7.7 
mW from the same substrate occu- 
pied by 0.25-um-geometry CMOS de- 
vices. Their paper is called “A high- 
performance epitaxial SiGe-base ECL 
BiCMOS technology.” 

In the same session, T. Lui, G. 


| Chin and other researchers at AT&T 


Bell Laboratories (Holmdel, Prince- 
ton and Murray Hill, NJ) show a 
0.5-um BiCMOS circuit with 31-ps ECL 
gate delays and 58-ps CMos gate de- 
lays. Their paper is called “A Half- 
Micron Super Self-Aligned Bicmos 
Technology for High-Speed Applica- 
tions.” 

However, the most practical paper 
in the Monday session on BiCMOS (as 
well as one of the most dramatic) 


| comes out of experience in smart 


power and RF circuits. Authors P. 
Tsui, P. Gilbert and S. Sun of Mo- 
torola (Austin, Tx) describe a way to 


| integrate 60-V lateral double-dif- 


fused MOS (LDMOS) on a BiCMOS sub- 
strate with 0.5-um devices and fis on 


| the order of 26 GHz. With luck, 


these structures will contribute to 
the portable RF transmitters of the 
near future. a 


© 1991 Brooktree Corporation. 


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ETECHNOLOGY DIRECTIONS 
INTEGRATED CIRCUITS 


Analog Devices courts designers 
with open architecture DSP 


Stephan Ohr, Contributing Editor 

he control and manipulation of 
T analog signals is certainly 
among the most fruitful uses of 
DSP technology. But because many 
DSP components were initially archi- 
tected as microcontrollers and re- 
quired extensive programming or 
coding, traditional analog designers 
were among the slowest to grasp the 
potential of this burgeoning technol- 
ogy. Apart from programming diffi- 
culties, there is also the issue of 
price. Many frequency filtering and 
timing-window control functions can 
be performed much more cheaply 
with a fistful of inexpensive analog 
components. 

Manufacturers of DSP components 
and development tools have tackled 
these problems head on. They’re im- 
proving the performance and push- 
ing down the cost of their compo- 
nents, while perfecting easier-to-use 
toolsets. And as a result they’re wit- 
nessing an exponential growth in 
the number of applications that take 
advantage of DsP solutions. 


_ H initiative proposed 


But the conversion process is far 
from complete. A recent Computer 
Design/Indian Forest Research sur- 
vey of analog and mixed-signal sys- 
tem designers found that far fewer 
than 50 percent were considering 
psP solutions. Many analog design- 
ers seem resistant to using DSP, and 
chip-set vendors are taking new 
steps to convince this group that DSP 
isn’t just some sort of fancy micro- 
processor. 


Against the possibility that real- 
world system designers are finding 
it difficult to choose among compet- 
ing DsP architectures and vendors, 
Analog Devices (ADI—Norwood, MA), 
an acknowledged leader in analog | 
signal-conditioning and data-con- 
version technology, has proposed 
what it calls a Signal Computing | 
Initiative. Like the cap Framework 
Initiative talked about by EDA tool | 
vendors, the Signal Computing Ini- 
tiative calls for an open architecture 


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Sample Rate vs Data Word Size | 


IMAGE | 


~# NON-REALTIME REALTIME —> 
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replacements for analog components. 


46 DECEMBER 1992 COMPUTER DESIGN 


The increasing bandwidth and precision of psp cores let them be utilized over a 
wide range of low- to high-end applications, says tis Kun Lin. The majority of 
these designs, however, are custom projects rather than off-the-shelf drop-in 


that lets designers mix and match 
DsPs, signal-port chips, drivers, and 
operating systems. Ideally, you can 
pick and run off-the-shelf compo- 
nents and algorithms for speech rec- 
ognition, audio and video image 
compression, and modem line 
conditioning. 

“Front-end ports geared for audio 
or telephone can be paired with DsPs 
from Analog Devices or Motorola,” 
says David D. French, Analog’s vice- 
president and general manager. 
“Nothing is proprietary.” 

Anticipating critics who may sug- 
gest that the Signal Computing Ini- 
tiative is a response to the domi- 
nance of competitors’ components— 
specifically those of Texas Instru- 
ments (Houston, Tx) and Motorola 
(Austin, Tx)—Analog Devices an- 
nounced an impressive series of de- 
sign wins at DSPx, a new conference 
and trade show dedicated to digital 
signal processing, in October. Com- 
puter maker Olivetti (Ivrea, Italy 
and Cupertino, CA), for example, 
uses the Analog Devices ADSP-2111 
processor and voice codecs to imple- 
ment digital voice recording and 
playback on its Quaderno portable 
pc. Siemens (Munich, Germany) 
uses the ADSP-2111 as a speech rec- 
ognition device for neural networks. 


| Lernout & Hauspie (Ieper, Belgium) 


and VTech Systems (Hong Kong) 
have gotten together on a talking 
multilanguage dictionary using the 
Analog Devices ADSP-2105, and 
Digianswer of Denmark will OEM 
digital answering machines and 
boards using ADI components. All 
these manufacturers have endorsed 
the Signal Computing Initiative. 


Bi still a custom business 

Yet, the true impact of a Signal Com- 
puting Initiative may not be felt for 
some time. It isn’t just that Analog 
Devices has a smaller number of de- 
sign wins than its competitors, which 
makes it a less powerful lobbyist for 
open systems. The acceptance of the 


| initiative may be limited more by the 


fact that the largest part of Dsp de- 
sign has been a customization effort 
requiring close coupling between sil- 


| icon vendor and customer. It’s only 


minimally a standard-parts business 
supported by off-the-shelf compo- 


nents and software. 


According to Kun Lin, DSP mar- 
keting manager for Texas Instru- 
ments, the company with by far the 


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CIRCLE NO. 33 


EPTECHNOLOGY DIRECTIONS 


- 


— 


largest proportion of psp design 
wins, the cpsP product line has been 
the most aggressive in driving down 


the costs of psp solutions. (The “c” in 


cpsP stands for “customizable.”) “In 
volume,” says Lin, “cDSsP can be 
lower in cost than a boardful of sep- 
arate analog and DSP components.” 


INTEGRATED CIRCUITS 


The cpspP line offers an ASIC meth- 
odology in which signal-conditioning 
components and A-D and D-A con- 
verters can be combined with C1X 
or C2X processor cores, versions of 
the TMS320 architecture, to provide 
parts with analog inputs and out- 
puts. The increasing bandwidth and 


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CIRCLE NO. 31 


48 DECEMBER 1992 COMPUTER DESIGN 


precision of the DSP cores, moreover, 
let them be used over a wide range 
of low- to high-end applications. 
But these are hardly drop-in re- 
placements for analog components. 
The specialized requirements of 
disk-drive manufacturers, for exam- 
ple, militate against the use of stan- 


' dard off-the-shelf components. Yet 


drive makers are gravitating toward 
DsP solutions to the problems of head 
positioning and spin control. 

The DsP core provides specialized 
acceleration and deceleration algo- 
rithms that ensure greater tracking 
ability with tighter track densities 
and shorter seek times. The analog 
inputs make it easy to read embed- 
ded servo bursts, while the analog 
outputs drive power transistors and 
motor coils. The cost of an integrated 
DSP solution won’t be competitive 
with the op amps and filters cur- 
rently used for this application, but 
the increased precision, reliability 
and lack of drift mean that the over- 
all cost of ownership is very reason- 


| able. For this reason, DSP ASICs are 
| finding their way into a wide variety 


of custom applications, including in- 
dustrial motor controls and digital 
answering machines. 


| Zilog prefers DSP ASICs 


Zilog (Campbell, CA) also supports a 
psp Asic methodology. Its Z89120 
modem controller, for example, con- 
sists of an 8-bit microcontroller, a 
16-bit DsP core and data converters 
geared toward pulse-width modula- 
tion. The part handles 9,600-bps mo- 
dem, fax and voice interactions be- 
tween a telephone line and a 
computer host. 

Bryant Wilder, Motorola’s psp 
operations manager, sees little need 
to court analog designs with drop-in 
solutions to applications currently 
served by analog components. 
“There are many applications which 
will benefit from [the]...programma- 
bility...precision and reliability of a 
DsP solution,” he says, “but it’s al- 
ways better to start with a clean 
sheet of paper.” Although there are 
psP chips that sell for less than $3, 
he adds that “You don’t get a lot for 
$3.” DsP becomes cost-effective in a 
design that was meant from its in- 
ception to offer high precision, reli- 
ability and programmability. 

The improvements in price-per- 
formance of DSP components, and es- 
pecially improved bandwidth, pave 


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CIRCLE NO. 30 


ETECHNOLOGY DIRECTIONS 


the way for applications that didn’t 
previously exist. In addition to suc- 
cesses in digital cellular telephone 
applications in Europe (and, in- 
creasingly, in the U.S.), Wilder points 
to the use of 56000 products in 
Sony’s newly introduced 5-4-in. 
erasable optical disk products. The 


INTEGRATED CIRCUITS 


56000 in these peripherals controls 
the focus and tracking of the optical 
laser. Because of their potential for 
drift with temperature, analog com- 
ponents could never provide the de- 
gree of control possible with a 24-bit 
psp. “Analog runs out of gas,” says 
Wilder, “but, with new psp technolo- 


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« TMS320C40, 'C30, 'C25, and DSP32C 
« A/D’s and D/A’s from 12 to 18 bits 
¢ Sampling rates to 10 MHz 
¢ Digital I/O and SCSI interfaces 
¢ T1/CEPT telecom interfaces 
¢ Precision clock generators 
« VMEbus, Multibus | or Il baseboards 
« MIX bus expansion modules 
¢ Bus adapters for SUN and PC-AT 


he right software. 


¢ Pentek SWIFT C development system 
¢ SPOX real-time OS and DSP libraries 


¢ Comdisco SPW DSP code generator 


¢ SUN UNIX and PC-AT Support 
¢ ProNet Ethernet system 
« DSP C compilers 


¢ Drivers for MIX modules 


Got a problem? 
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CIRCLE NO. 28 


50 DECEMBER 1992 COMPUTER DESIGN 


| gies, we have the opportunity to con- 
vert a $500 or a $1,000 system into 
| a $50 or $100 board.” 


Bl Success at Star 


As it turns out, the success of Star 
Semiconductor (Warren, NJ) in win- 
ning over analog designers to DSP 
solutions is related more to its abil- 
| ity to customize parts for an applica- 
tion than it is to any low-cost drop-in 
replacement. While similar to the 
Motorola 56000 in capabilities (in 
that it provides 24-bit fixed-point 
processing), the architecture of 
Star’s SprocChip is totally customiz- 
able by the user. Unlike micro- 
| processors, which need to be pro- 
grammed, SprocChips can be 
specifically crafted for analog appli- 
cations. These chips are like PLDs for 
analog—the program is the architec- 
ture. And Star’s pc-based develop- 
ment tools are intended to make the 
programming job easy. This start-up 
company now has an impressive 
number of design wins among com- 
munications and audio equipment 
manufacturers. 

These design wins are due more 
to the ease-of-use of the architec- 
tural development tools, however, 
_ than to price or other factors. While 
the company is working toward a 
| $25 part, current versions of the 
| SprocChip are in the $100 range, 
and they’re targeted toward the 
same applications that TI and Mo- 
torola say they can do for $10. 

While psp offers innovative solu- 
tions to the problems of interfacing 
| electronics to the real world, the de- 
signer’s preference for custom DSP 
may seem to negate the multivendor 
drop-in solutions proposed by 
Analog Devices. And while “cost-ef- 
fective” is a part of the company’s 
vocabulary, if analog design is to be 
synonymous with “cheap,” DSP ven- 
dors still have a way to go. | 


For more information about the technol- 
ogies, products or companies mentioned in 


this article, call or circle the appropriate 
number on the Reader Inquiry Card. 


Analog Devices 


NAPUS NSA 2 tu rao an thaw aie y Circle 204 
Motorola 

(512) 891-2030 Circle 205 
Star Semiconductor 

(703) 689-4400 ....... .Circle 206 
Texas Instruments 

(713) 274-2320 ....... . Circle 207 
Zilog 

(408) 370-8000 .... . Circle 208 


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CIRCLE NO. 29 


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PTECHNOLOGY DIRECTIONS 


SOFTWARE & DEVELOPMENT TOOLS 


Alliances to speed acceptance 
of fuzzy logic technology 


Tom Williams, Senior Editor 
s fuzzy logic gains acceptance 
A as a viable technology for em- 
bedded control, alliances are 
starting to form between large mer- 
chant semiconductor companies and 
smaller companies that were ex- 
pressly founded to develop and mar- 
ket fuzzy logic software and hard- 
ware. Most of the latter companies 
are moving from being primarily 
consulting and custom engineering 
firms to becoming vendors of soft- 
ware development tools and dedi- 
cated fuzzy processor designs. 
Motorola (Schaumberg, IL), for ex- 
ample, has formed an alliance with 
Aptronix (San Jose, CA), which is 
making the transition from engineer- 
ing consulting and design to vendor 
of its new Fuzzy Inference Develop- 
ment Environment (FIDE) product. 
FIDE, which will be jointly marketed 
by the two companies, includes edi- 
tors for fuzzy membership functions 
and rule sets, three types of debug- 
ging tools, a composer tool for link- 


ing modules created under FIDE with | 
other C programs, and assembly 


code generators. The current ver- 


sion of the product directly supports | 


Motorola’s MC6805 and 68HC11 8- 
and 16-bit microcontrollers. 
Intel (Chandler, Az) has also ar- 


ranged a partnership with Inform | 


GmbH (Aachen, Germany and 
Evanston, IL). Inform offers a fuzzy 


logic development system called | 


fuzzyTECH. FuzzyTECH supports 


graphical editors for the fuzzy rule | 


base, as well as for membership func- 
tions, and it provides an interface for 


graphically simulating designs. The | 
development tool generates C code | 


and optimized assembler code for se- 
lected microprocessors. In collabora- 
tion with Intel, Inform is supplying 
a version of fuzzyTECH, Release 3.0, 
that directly supports Intel’s 8xC196 
line of 16-bit microcontrollers. 

One of the unique features of fuzzy- 
TECH is its online editing capability. 
With a serial line, you can modify 
the membership functions or rules 
of a running system through the 


graphic editor, and then you can di- | 


rectly observe the results in system 
behavior. Further, the Inform prod- 


uct supports the integration into de- 
signs of neural net technology. This 
feature may come in handy, given 
Intel’s recent activity in neural net 
processors—such as its 80170NX 
analog neural network chip and Pc- 
based neural training software. 

For initial evaluation, Inform 
supplies a $199 Explorer version of 
fuzzyTECH that features limited 
functionality. You can create sys- 
tems with 2-input and 1-output var- 
iables and up to 5 labels (or mem- 
bership functions) per variable, as 
well as one rule block with 125 
rules. The Explorer outputs C code 
that can be integrated into some 
applications. 


Bf Hardware/software partnerships 
Dedicated fuzzy logic companies 
that have developed designs for 
processor chips, such as Togai Infra- 
logic (Irvine, cA) and American 
NeuraLogix (Stanford, FL), have 
been contracting with silicon found- 
ries to produce their designs. But 


both these companies have also 
signed licensing agreements with 
semiconductor companies for the 


| use of their fuzzy processor designs 
| as core technology. 


American NeuraLogix, for exam- 
ple, has signed a 10-year technology 
transfer agreement with Samsung 


| (Seoul, Korea) that gives the Korean 


company manufacturing and use 
rights to NeuraLogix’s core chip 
technology. Central to that technol- 
ogy is the NLX230, a high-speed, 
low-cost 8-bit fuzzy microcontroller. 
The NLX230 and its newly en- 
hanced version, the NLX231, are 
both capable of about 30 million rule 


| evaluations per second and contain 


hardware-defined membership 
functions, fuzzifiers and defuzzifica- 
tion options. The agreement with 


| Samsung is seen as a way to accel- 


erate the migration of fuzzy logic 
into a wide variety of products. 

NeuraLogix supplies a software 
tool specifically aimed at program- 
ming its processor products. The tool 
comes with an AT-compatible devel- 
opment board containing an 
NLX230. The NLX231 is downward- 
compatible with the NLX230 but 
contains more options and can hold 
more rules. 

Togai Infralogic offers a full line of 


FIDE_EZ Linker 


File” Edit Graphics Make Run 


al | 


c\fide-ez\apt.gnk 


= 


Ts 


124 


ix] 


Feut—12/7 


\44 


7 pstepi 


Ea 


a a 


Aptronix’s Five includes a facility called Composer, which can be used to graphically 
link fuzzy inference units (rius) to C code modules from existing or conventional 
applications. This process generates applications containing a combination of 


conventional and fuzzy logic code. 


52 DECEMBER 1992 COMPUTER DESIGN 


Learn the Only Embedded Debugger You 
Will Ever Need Without Turning the Page 


TARGETS: 


68xxx, 386/486, R2000/R3000/R4000, 
Sparc, 88000/88110, Gmicro, V810, more... 


C + C++ © Fortran ¢ Pascal 


Double click on a variable 
to create a window that 
displays its value when- 
ever the program stops. 


Click on a variable to print 
its value. 


Click on a green dot to set 

3 a breakpoint. Click on the 
stop sign to clear the 
breakpoint. 


The program is currently 
stopped here. 


i+ at 


struct bag { 
struct bar *next; 


float d[10]; 
int count; 
}*Bar; 


ct bar *NewBar(count,color) 
enumcolor color; 


enum color {red,orange,yellow,green,blue}color; 


Click here to 
see the object 
this points to. 


Double click here 
to see this array 


0, 1,2,3,4,5.,... 


in a new window. 


Move the mouse 
here and type in 


| 10< 


a new value. 


ret = (struct bar *)malloc(sizeof(struct bar)); 


_ | 57 ¢  ret->next= NewBar(count-1,color); 
58 ¢ ret->color = color; ——— = = ¥ = z 
5 Click on a function oe | | \ 59 ¢  ret->count = count; | I boi ener e J 
to display its source code. {\| \60 ¢ for (i=0;i<ount; i++) | 0_NewBar(count= 10,color=orange( 1 )) | 
| 6laamm ret->d[i] =i; * 1_main( i} 
62 ¢ return ret; —— =a! 
| rs } 


Attach to a target with the | 
"remote" command. 


Set a conditional break- 
point at the current line. 


Click “go” to continue (or 
start the program). 


Click 
register view window. 


Click “help” to learn 
the rest of MULTI. 


“reg” to display at = 


[stops IL regs at local it pop | 


Click “calls” to 

display a call 

stack window. 
Click “halt” to 


stop execution 
of the program. 


Click “edit” to 
edit the current 
function. 


Click “assem” to 
+ display interlaced 
source/assembler. 


It’s worth learning MULTI to to fix one bug. 


Hosts: Microsoft Windows, 8 Sun-3, DECstation, Unix/386, Motorola Delta, more.. 


will las i, 


se 
reen Hills ae 
“SOFTWARE. INC. ¢ 
$10 Castillo, Santa Barbara, CA 93101 1 Cranberry Hill, Lexington, MA 02173 
Tel: (805) 965-6044 ¢ FAX: (805) 965-6343 Tel: (617) 862-2002 © FAX: (617) 863-2633 


Copyright 1992 Green Hills Software, Inc. MULTI and Green Hills Software are trademarks of Green Hills Software, Inc. All other trademarks are trademarks of their respective owners. 


CIRCLE NO. 34 


ETECHNOLOGY DIRECTIONS 


SOFTWARE & DEVELOPMENT TOOLS 


fuzzy logic software development 
tools and hardware. Its FC110 fuzzy 
processor is available as a chip or 
integrated on board-level products 
for AT, VME and Multibus. Togai also 
offers a line of software development 
tools, of which the centerpiece is 
TILShell. TILShell is a Windows- 
based graphical development envi- 
ronment that lets you edit and 
debug membership functions and 
rules. It interfaces directly to pack- 
ages that generate code for the 
FC110, MicrorrL code that can be 
run with an interpreter for a wide 
selection of 8- and 16-bit micro- 
processors, and a C code generator. 
In addition, Togai offers TILGen, a 
package that uses neural network 
technology to analyze a system’s in- 
puts and generate a rule base. 
Most recently, Togai has intro- 
duced a core cell technology called 
FCA (fuzzy computational accelera- 
tion). The FCA core can be implemen- 
| ted in a range of sizes, from 8 to 32 
bits, and can be used as a stand- 
_ alone processor, integrated on a chip 


Neufuz block diagram 


APPLICATION 
PARAMETERS 
ee 
SYSTEM INPUT/OUTPUT 
DATA 

oe 


FUZZY RULES 
AND 
MEMBERSHIP 
FUNCTION 
GENERATOR 


NEURAL 
NET 
LEARNING 


MEMBERSHIP FUNCTIONS 


FUZZY RULES 


MICROCONTROLLER 
ASSEMBLY CODE 


esas eae Mal 


SYSTEM INPUT DATA 


Neufuz from National Semiconductor uses the input/output data along with the pa- 
rameters specified for the system under development to automatically generate fuzzy 
rules and membership functions—and, ultimately, the application code. The devel- 
oper works by converging the design on the expected behavior of the system and 
then verifying it, but he or she won't see the intricate detail of the internal workings. 


We Give ( 0 To Our Customers. 


Whatever it takes, at 
Mitsubishi we’ll go the 
extra mile to help our cus- 
tomers meet their memory 
card needs. 

That means onshore applications 


Our dedication to 110% customer 
support is why we maintain well-stocked, / 
onshore inventories, totally automated / 
shipping services, and inventories 
available through authorized 
Mitsubishi Electronics America, 
Inc. stocking reps and distributors. 


engineering, marketing and sales support. 
It means we'll support your custom card, 
custom panel artwork and programming 
requirements, as well as provide cards 
that meet current PCMCIA, JEIDA 

and JEDEC standards. 


54 DECEMBER 1992 COMPUTER DESIGN 


When it comes to memory cards, 
we're here when you need us. We follow 
up. We solve problems. We give 110%. 


2. MITSUBISHI 


Call (408) 730-5900, ext. 2214. ELECTRONIC DEVICE GROUP 


CIRCLE NO. 35 


DISTRIBUTED PROCESSING 
WITH THE QNX® FLEET™ NETWORK. 


BECAUSE COMPUTERS WERE MEANT TO RUN TOGETHER. 


Maybe it’s not natural to expect 
a network of microcomputers to 


perform like a supercomputer. 


With the QNX operating system, 
it’s not natural to expect 
anything less. 


POSIX AND MORE 


Thousands of VARs and OEMs 
choose QNX for mission-critical 
applications — from POS to 
manufacturing to medical 
instrumentation. 


And with good reasons. 


Like POSIX compliance. 

And real realtime performance. 
And true microkernel architecture. 
And message-passing IPC. 

Not to mention our technical 


support and customer services. 
Now add “FLEET” to the list. 


FAULT-TOLERANT 
NETWORKING 


With most networks, 

a hardware failure spells disaster. 
But not with QNX. 

Ifa card or cable fails on 

a dual-net FLEET setup, QNX will 
automatically re-route data 
through the other network 

before you — or your application — 
can even blink. 


LOAD-BALANCING 
ON THE FLY 


For greater throughput, 
the FLEET network puts all 
available network hardware 
to work at the same time. 
And it will dynamically 
distribute the load by choosing 
the best route for the job. 


EFFICIENT PERFORMANCE 


FLEET uses network hardware 
to full advantage for maximum 
throughput. Whether you're 
running Ethernet for speed 
(application-level throughput 
at just under 1 Mbyte per second) 
or Arcnet for deterministic 
transactions — or both 
network cards in the 
same machine — you can count 
on FLEET for optimum efficiency. 


REALTIME OPERATING SYSTEM 


CIRCLE NO. 36 


EXTENSIBLE 
ARCHITECTURE 


You can support new networks 
simply by adding new drivers. 
And you can start and 

stop drivers dynamically, 


without even rebooting. 


TRANSPARENT 
DISTRIBUTED 
PROCESSING 


In QNX there’s no difference 
between local execution and 
network-remote execution. 
Which means you don’t need to 
modify your applications in order 
to distribute them across 

the FLEET network. 


To sum up: networking 
with QNX is fault-tolerant, 
load-balancing, efficient, 
extensible, and transparent. 
But it’s a lot easier 

to just say “FLEET.” 


Go with the QNX FLEET network. 
Nothing runs like it. 


To find out how your 
applications can thrive in 
the QNX environment, 
call 1-800-363-9001 
(ext. 103). 


ETECHNOLOGY DIRECT 


IONS 


SOFTWARE & DEVELOPMENT TOOLS 


with a conventional processor core, 
or put on a chip with custom logic. 
Different mixes of rule-base and 
scratch-pad memories can be incor- 
porated as well. 

Togai has entered into two agree- 
ments, one with visi Technology 
(San Jose, CA) and another with Hi- 


tachi America (Brisbane, CA). The 
agreement with VLSI has resulted in 
the first implementation of a func- 
tional system block (FsB) for fuzzy 
logic applications. It’s a 12-bit imple- 
mentation of the FcA technology 
that’s been dubbed the VY86C500, 
and it’s capable of some 850,000 rule 


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CIRCLE NO. 37 


56 DECEMBER 1992 COMPUTER DESIGN 


evaluations per second at 20 MHz. 
The fuzzy FSB can be combined with 
other microprocessor FSBs to form 
complete conventional/fuzzy proces- 
sor units for embedded systems. 

Togai’s agreement with Hitachi 
America covers the use of fuzzy logic 
on conventional microcontrollers, 
primarily Hitachi’s H8. It also in- 
cludes support for training, docu- 
mentation and hardware evaluation 
products, as well as for adapting 
software development tools to use 
with Hitachi processors. 


| Going it alone 


The one US. semiconductor vendor 
that seems to be going it alone is 
National Semiconductor (Santa 
Clara, CA). National has set out on 
an ambitious project to develop fuzzy 
logic products simultaneously with 
neural network technology. It will 
soon be introducing a development 
tool called Neufuz. As this software 
technology matures, National plans 


_ to migrate it into silicon products. 


Neufuz uses neural net learning 
to non-heuristically generate fuzzy 
rules and membership functions, at 
the same time using only the speci- 
fications of the system—that is, 
which outputs are expected from 
what inputs. The neural net learns 
by converging the inputs and out- 
puts with the application parame- 
ters, after which its output is used 
to generate fuzzy rules and member- 
ship functions. These are run 
through a proprietary rule verifier 
and optimizer and eventually gener- 
ate assembly code. € 


For more information about the technol- 
ogies, products or companies mentioned in 
this article, call or circle the appropriate 
number on the Reader Inquiry Card. 


American NeuraLogix 


(407) 322-5608 Circle 209 
Aptronix 

(408) 428-1888 Circle 210 
Hitachi America 

(415) 589-8300 Circle 211 
Inform GmbH 

(708) 866-1838 Circle 212 
Intel 

(602) 554-2374 Circle 213 
Motorola Microprocessor Division 

(708) 576-7000 Circle 214 
National Semiconductor 

(408) 721-5000 Circle 215 
Togai Infralogic 

(714) 975-8522 Circle 216 
VLSI Technology 

(213) 931-0009 Circle 217 


So you think you can 


design a better embedded 


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CIRCLE NO. 38 


ETECHNOLOGY DIRECTIONS 


Warren Andrews, Senior Editor 
ewlett Packard (Colorado 
Springs, CO)has just joined 


4 the growing cadre of work- 
station makers bidding for the real- 
time industrial market. It follows 
closely on the heels of Digital 
Equipment Corporation, which an- 
nounced its entry into the realtime 


market with a VMEbus-based ap- 
proach and a POSIX 1003.4-compat- 


(RTOS). HP’s announcement last 
month introduced a whole family of 
new products coming from its 
Measurement & Control Systems 
Division, a new unit that focuses on 


the needs of the factory floor, as | 


well as control applications in man- 
ufacturing, aerospace, telecom, 
and commercial electronics. In ad- 


and boards, HP also debuted the 
HP-RT RTOS for its hardware. 

At the center of HP’s thrust is the 
company’s PA-RISC 7100 processor. 
(PA stands for Precision Architec- 
ture.) The 50-MHz version of the 
chip set lets systems operate at 61 
Mips and betters 60 spECmarks in 
performance. But that’s only part of 
the story—HP has boarded the vME- 
bus in a big way, announcing three 
major VMEbus board makers as com- 
plementary hardware vendors 


bus trade association, VITA, as a se- 
nior member. 


Bf The VME alternative 


While there’s been much discussion 
of Futurebus+ as the latest-genera- 
tion backplane bus for a variety of 
applications, including industrial 
automation, communications and 


ported vMEbus for industrial appli- 


ber of vendors offering Vo for VME, 
recent activity within the trade 
group pushing the bus to higher ley- 
els of performance should keep it 
viable for a number of years. 

First, the addition of VME64 
doubled the effective bandwidth of 
the bus, and the possibility of using 
a source-synchronous transfer pro- 
tocol holds promise for yet another 
twofold increase in performance. 


58 DECEMBER 1992 COMPUTER DESIGN 


ible realtime operating system | 


dition to industrial workstations | 


(CHvs) and signing on with the vME- | 


aerospace, it’s interesting that both | 
HP and Digital have heavily sup- | 


cations. Aside from the large num- | | 


Now, it looks as if a viable live-inser- 


tion technology is available, and pro- | 


totypes will soon be up and running. 
Future enhancements, including the 
addition of a number of serial lines 


to the P2 connector, promise to bring | 


VME up to the performance level that’s 
now the domain of Futurebus+. 

While HP is firmly backing VME as 
its industrial platform, it still hasn’t 
abandoned its other approaches. In 
announcing its realtime strategy, 
the company mentioned a pair of 
box-level workstations, as well as its 
742rt VME board-level product. Both 
of its box-level products support the 
EISA bus. One of them, the 745i, has 
four EISA slots. The other, the 747i, 
offers a combination with two EISA 
slots and six vMEbus slots. 

The two workstations are binary- 
compatible with the company’s S700 
and most current S800 systems, let- 
ting them run many applications 
| currently supported on HP’s UNIX 

platform, HP-Ux. These applications 
| include a variety of specialized man- 

ufacturing automation tasks, as 
well as database applications and 
office productivity tools. 

The company’s major VME offer- 
ing, however, is the 742rt 6U VME 


| architecture, Hp-RT. 


Featuring all-front-panel vo, Hewlett Packard’s HP9000 Series 700rt, model 742rt, 
is a 6U vmebus card that occupies two vme slots. Its 50-MHz np pa-risc chip set gives 
| itmore than 60 Mips, one of the most powerful vme cpus to date. It includes standard 
ceu features such as serial and parallel port, Ethernet and SCSI-2 ports, and comes 
with a run-time copy of HP's latest realtime operating system designed for the pa 


COMPUTERS & SUBSYSTEMS 


HP debuts VME, realtime solutions 


board. Designed as a single-board 
system, the 742rt takes up two VME- 
bus slots and boasts one of the high- 
est performance ratings of any VME 
CPU, topping off at 61 Mips. It differs 
from most competitive products in 
that it offers Ecc memory (8 Mbytes 


| standard, with 16, 32 and 64 Mbytes 


optional) in place of parity-protected 
memory. According to HP, this type 
of memory detects and corrects sin- 
gle and multibit errors, providing a 
more reliable system than a parity- 
protected approach. 

The vME card has all Vo coming off 
its front, as opposed to systems with 
yo connection off the card itself or off 
the P2 connector. Like most CPU 
cards, HP’s 742rt has a variety of 
built-in Vo, including a pair of RS- 
232 ports, a parallel port, Ethernet, 
and SCSI-2. 


B HP-RT completes the picture 
The 742rt includes a run-time li- 
cense for HP’s realtime operating sys- 
tem, HP-RT. Unlike Digital, which se- 
lected a third-party rTos, Wind 
River’s VxWorks, to modify for its 
processor, HP has built its own oper- 
ating system. 

Designed to be posix 1003.1-, 


INTRODUCING THE TP810V 
TADPOLE’S HIGH-PERFORMANCE COMPUTING ENGINE FOR REAL-TIME APPLICATIONS 


200 MIPS and VME;-64 


Real-Time Performance. 


No Compromises. 


When we designed the 
TP810V, we approached it with 
total system performance in 
mind. With state-of-the-art 
microprocessors, high-speed 
memory, the latest generation 
I/O components, VME-64 and 
optimized real-time software, 
nothing gets in the way of 
information throughput on the 
TP810V. 


Issuing up to 2 instructions 
on every clock, Motorola’s 
88110 Symmetric Superscalar™ 
RISC microprocessors provide 
the TP810V’s horsepower. 
With dual 50 MHz 88110 


3 A 


microprocessors”, the TP810V 
achieves overall system 
performance of up to 200 MIPS/ 
200 MFLOPS — that’s an 
impressive $50/MIPS. 


Memory options include 
1 MB of high-speed synchro- 
nous SRAM with a sustained 
bandwidth of 228 MB/s and an 
expansion board with up to 
128 MB DRAM. The TP810V 
accesses the additional DRAM 
at sustained on-board memory 
speeds of 133 MB/s. 


And because cache 
coherency is essential for 


Computing Without Compromise 


p 


D 


maintaining 

performance in 
multiprocessor systems, we've 
built in bus snooping support 
— even for the VME-64 
interface. 


The TP810V uses the latest 
in controller technology to 
eliminate common I/O 
bottlenecks: you can choose 
from two standard I/O modules 
with a 32-bit Ethernet 
controller and either one or 
two Fast and Wide SCSI-2 
controllers. If neither of these 
options fit your system 
requirement, we'll design a 


O 


CIRCLE NO. 39 


custom module to your 
specifications. 


To complete the system, the 
TP810V supports Integrated 
Systems’ pSOSystem™, the 
modular real-time operating 
system with transparent 
multiprocessing capability. And 
with high-level language 
compilers readily available for 
the 88110 microprocessor, you 
can shorten your product 
development cycle without 
sacrificing performance. 


If you're looking for a real- 
time computing engine with 
superb overall system perfor- 
mance at a great price, take a 
look at the TP810V. We think 
you'll like what you see. 


Call Today For A Free Brochure 


800-232-6606 


FAX 512-219-2222 


“Single processor TP810V models are also available. 


ETECHNOLOGY DIRECTIONS 


COMPUTERS & SUBSYSTEMS 


1003.4- and 1003.4a-compatible, HP- 
RT is designed from the ground up to 
provide hard realtime capability 
tuned to the HP PA-RISC platform. A 
native POSIX application program- 
ming interface (API) is implemented 
for system calls, realtime extensions 
and process threads. The os also 
incorporates some of the best UNIX 
features, including protected ad- 
dress spaces, multiprocessing and 
graphical user interfaces, into HP-RT. 

In addition, HP-RT can be scaled to 
balance memory and performance 
requirements. With a small kernel, 
overhead is kept to a minimum, and 
optional services can be invoked as 
required. The OS complies with the 
POSIX 1003.1 standard, and it follows 
the posix 1003.4 draft 9/10 for real- 
time extensions, as well as the PosIx 


1003.4a draft 3/4 for process-level | 


threads. POSIX compliance has re- 
mained an elusive thing for realtime 
extensions because of the rapidly 
changing drafts. Some vendors have 
elected to use a particular draft, 
such as draft 4, rather than continue 
to shoot at a moving target. (The 


current version, which is under- | 
going the approval-or-rejection cy- | 


cle, is draft 10.) The HP-RT includes 
many SVID/BSD commands and sup- 


ports C, ANSI C, C++, and PA-RISC as- | 


sembly. 


B Third parties party on 


While both Hp’s box-level worksta- 
tion products have at least some EISA 


capability, the company’s support of 


VMEbus is emphasized with an in- 
dustry-leading cPpU, membership in 
industry trade groups and its third- 
party agreements. The latter in- 
clude arrangements with the cmc 
Network Products Division of Rock- 
well International (Santa Barbara, 
CA), SBE (Concord, CA) and VMIC (VME 
Microsystems International— 
Huntsville, AL). 

According to Hewlett Packard, 
cmc has been selected as a CHV to 
provide Ethernet and FDDI VMEbus 
local-area network connectivity for 
its realtime industrial workstations. 
cmc plans to work closely with HP to 
supply the necessary drivers for 
both HP’s realtime and UNIX operat- 
ing systems. 

SBE will be offering HP’s OEMs and 
integrators its eight-port VCOM-34 
X.25 controller, with eight high- 
speed serial ports in a single VMEbus 
slot. Its eight full-duplex, inde- 


pendently programmable serial 
channels can transmit and receive 
asynchronous, X.25-compatible 
HDLC and bisynchronous protocol 
data at E1 (2.048 Mbps) rates. sBE’s 
VCOM-34 card includes an on-board 
68030 processor to ease the burden 
of the HP PA-RISC processor. 

The company will also provide its 
VPU-25 intelligent vo controller to 
handle a variety of 0, memory and 
custom options. The board is meant 
for OEMs requiring a high-perfor- 
mance interface between VME sys- 
tems such as a mini/super minicom- 
puter and wide-area networks or 
other applications requiring high- 
speed point-to-point data transfer. 
Serial interface modules let each 
port be separately configured for 
EIA-232-C, EIA-422, EIA-449, EIA- 
530, X.21/V.11, or V.35 standards. 

VMIC will offer a variety of /O prod- 
ucts, including host adapters, VME- 
to-VME links, repeaters, reflective 
memory, digital and analog vo and 
synchro/resolver 1/0. Transition pan- 
els, power supplies, chassis, and 
other supporting products will be 
offered as well. 

With both up and Digital making 
firm stands in favor of VME in the 
industrial-control and factory-auto- 
mation arena, it seems that the VME 
standard is likely to continue its 
dominance in this area. With the 
inclusion of HP’s PA-RISC, every major 
RISC architecture now has strong 
VME support—with the exception of 
IBM’s RS/6000. SPARC is represented 
by, among others, Force, Themis and 
Tronics. « 


For more information about the technol- 
ogies, products or companies mentioned in 
this article, call or circle the appropriate 
number on the Reader Inquiry Card. 


CMC 

(805) 968-4262 E Circle 218 
Hewlett Packard (U.S.) 

(800) 637-7740 Circle 219 
Hewlett Packard (Canada) 

(800) 387-3867 Circle 220 
SBE 

(800) 347-2666 Circle 221 
VMIC 

(800) 322-3616 Circle 222 


60 DECEMBER 1992 COMPUTER DESIGN 


Looking for 
more than a 


sales pitch at 
Buscon West? 


When you visit Radstone 
Technology at Booth #826 
this February, you'll meet 
more than just a sales rep. 


We think Buscon should be a 
source for information, and 
exchange of ideas, on the 
technology and the industry. 
And, most of all, solutions to 
your problems. 


Come talk to the: 

e President 

e V.P. Sales 

¢ Director of Marketing 

e Engineering Manager 

e Marketing Manager, 
Product Technology 

¢ Senior Applications 
Engineers 

¢ Regional Sales Managers 


Oh yes, and lots of very 
knowledgeable sales reps too! 


So if you’re looking for some- 
one you can really talk to 
about VME, visit Radstone at 
Buscon/93-West. We'll make 
it worth your while. 


ate 
RADSTONE 


T: EG, BEN OnEL@ Gay 


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for Any VME Board! 


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re eos tO 
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Count on Radstone to deliver real world solutions to 
all your VME system needs. Need to insert or remove 
a board without powering down the system? The HS-1 
is ready today to add this live insertion capability to 
your existing VME boards. No smoke, mirrors or 
complications. Just a clean, clever solution. 


¢ Works with any standard VME board and backplane 

¢ Lets you use off-the-shelf hardware to configure 
your system 

¢ Provides controlled ramp up/down of power rails 

¢ Assures complete isolation of the VMEbus from the 
board during power up/down sequences 

e Automatically links daisy chain signals when a board 
is absent 

e Sub-nanosecond delay times for all pertinent 
VMEbus signals 


Radstone’s done it again... this time with live insertion. 
Let us do it for you. Call or write for the details. 


Radstone Technology Corporation 

20 Craig Road, Montvale, NJ 07645-1737 
Call Toll-Free: (800) 368-2738 

Eastern Region: (201) 391-2700 

Central Region: (708) 304-0202 

Western Region: (408) 727-4795 


CIRCLE NO. 40 


BUSCON/93-WEST 
See us in booth #826 


T EC H NOL ONG ¥ 


ETECHNOLOGY DIRECTIONS 


COMPUTERS & SUBSYSTEMS 


* 


Image processing gets price-performance boost 


Warren Andrews, Senior Editor 
ecause most image processing 
applications are too narrow 


Be for sales volume to reach even 


a minimum payback level, solutions 
have remained expensive and pro- 


prietary, or they've been composed | 
of large and bulky collections of stan- | 


dard and custom boards assembled 

to satisfy a specific application. 
Now, next-generation hardware 

from Datacube (Danvers, MA) takes 


advantage of finely tuned asic tech- | 


nology to cut size and cost while sig- 
nificantly boosting performance. At 
the same time, the modular architec- 
ture of the hardware, based on a tech- 
nology called vsiM (Virtual Surface 
Image Memory), lets it accommodate 
a broad variety of applications while 
using relatively standard, low-cost 
components. VSIM is similar in ap- 
proach to the company’s Max- 
Video 20 board, but the new 
module has a far larger mem- 
ory capacity, as well as on- 
module processing circuitry. 

At the heart of each module 
is a 225,000-gate Asic Datacube 
calls the D52. Not only does it 
manage image pipelines and 
perform many image process- 
ing tasks, but it lets the system 
use relatively inexpensive 
standard DRAMs in place of 
more costly multiported video 
RAMs. Each module can support 
multiple 40-MHz image pipe- 
lines and virtual memory, and 
each includes integral ALU, 
crosspoint, look-up table, and 
statistics. 


a Development and target 
The modules will be the heart 
of a new MaxVideo vMEbus 
board that Datacube will in- 
troduce early next year. A fol- 
low-on to the MaxVideo 20, it 
will be known as the Max- 
Video 200. Datacube has al- 
ready released the product’s 
development platform, the 
Maxtp, which includes the 
new board, and will be availa- 
ble this month. 

The development platform 
comprises a 5-slot VMEbus 
backplane; a Motorola 


MVME167 68040-based cPU; 


a MaxVideo 200 with a full comple- 
ment of modules and 24 Mbytes of 
on-board virtual image memory; 
and Lynx’s realtime operating sys- 
tem, Lynxos, with X-Windows and 
Motif; and a scsi hard disk, all in- 
stalled in a compact enclosure. In 
addition, MaxtTp provides a tape 
backup unit, keyboard and mouse. 
The MVME167 supplies many of the | 
housekeeping functions and pro- | 
vides industry-standard serial and 
parallel ports, as well as support for | 
Ethernet, scsi and video 1/0. MaxTp 
is designed to be a superset of what- | 
ever target system a particular ap- 
plication calls for. 

“We selected Lynxos,” 


says 


Datacube marketing services man- 
ager David Wright, “because it has | 
the look and feel of Sunos, with | 


which many developers are familiar. 
It also provides modular services so 
that developers can select as little as 
a basic kernel, or the entire Os, or 
only as many services as are re- 
quired.” 

The object of the development/tar- 
get environment is to let you assem- 
ble an application using the hard- 
ware platform along with the 
company’s software tools, which in- 
clude an interactive graphical user 
interface and a library of acceler- 
ated image-processing functions 
called sm@L (Standard Imaging 
Layered Library). 

picir (Datacube’s Interactive 
Graphical Imaging Tool) is one of the 
software tools, comprising an inter- 
active X-Windows- and Motif-based 
application that helps you quickly 
develop image-processing 
code. It eliminates lengthy 
editing and compiling cycles 
by letting you simply point 
and click on desired image- 
processing functions. 

And when combined with 
SILL, DIGIT helps you develop 
and check high-performance 
C-callable functions and com- 
plete applications in an inter- 
active environment without 
having to recompile at each 
stage. SILL and DIGIT are lay- 
ered on top of, and are com- 
patible with, Datacube’s Im- 
ageFlow language for 
pipelined processors. 

The object of MaxTp is to 
supply a full, rich develop- 
ment environment from 
which components can be 
added to an economical, high- 
performance target system. 
Target systems can be ROM-, 
disk- or network-based and 
can range from simple sys- 
tems with few operating ser- 
vices and peripheral devices 
to complex hardware systems 
with all os features. 


The vsim and the D52 at its heart are the brainchild of 
Datacube’s principal design engineer, Shep Siegel, who 
says “It's the first 40-MHz image processor on a single 
chip.” The asic not only speeds data on and off the new 
module, but also provides a large virtual memory and in- 
tegral on-chip processing functions, permitting the use 
of relatively inexpensive DRAM. 


B ASIC is key 

The third generation of 
Datacube’s MaxVideo tech- 
nology, the D52 and its asso- 
ciated vsIM technology ad- 


62 DECEMBER 1992 COMPUTER DESIGN 


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This timing based, 12 state, event driven simulator with support utilities 
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CIRCLE NO. 41 


BTECHNOLOGY DIRECTIONS 


COMPUTERS & SUBSYSTEMS 


vance the company’s resolution-in- 
dependent, region-of-interest (ROI) 
concept, providing faster pipelines, a 
virtual memory and the capability to 
perform a variety of processing steps 
on each stage of the pipeline. 

“The D52 is fabricated on a 
225,000-gate sea-of-gates array in 


0.8-Lum CMOs capable of handling in- 
put, processing and output at 40 
MHz,” says the company’s principal 
design engineer, Shep Siegel. “It’s 
the first 40-MHz image processor on 
a single chip.” With the capability to 
handle multiple frame memories, 


and with its own ALU, LUT and other 


SuperCard i860-based vector processors deliver. With our Quad-860 multiprocessor 
and our SC-3XL ultimate performance models, CSPI continues to offer you the greatest 
range of vector processing power. Look what you can get on a 6U board with VME64: 


features, it can off-load many func- 
tions from other parts of the system 
to permit a more compact implemen- 
tation of complex systems. 

The flexible architecture lets mul- 
tiple VSIMs be wired in parallel, re- 
sulting in even greater pipeline 
bandwidths. Because much of the 
processing can now take place in the 
40-MHz pipeline of the D52 chip, it’s 
possible to provide functions that 
are difficult, if not impossible, to im- 
plement at the board level, because 
of buffer delays and interconnect 
capacitance. 

By implementing virtual memory, 
the system can support image ar- 
rays that are larger than the 
amount of physical memory availa- 
ble, and so it can easily handle com- 
plex applications. The D52 can ad- 
dress a virtual memory space of up 
to 96 Mbytes. In addition, vsIm mod- 
ules can handle 40-Mbyte/s block 
transfers into and out of the module 
simultaneously. 


B Diverse applications 


Datacube has found wide-ranging 
applications for its technology, from 
image-enhancing systems for re- 
mote inspection of objects in hostile 
environments to controlling robotic 
equipment in food-processing opera- 
tions. The company’s systems are 
even used in high-level prepro- 
cessing applications for images that 
will later be worked on with high- 
powered DsP or even Cray-type su- 
percomputers. 

“But the bottom line,” says Siegel, 
‘is that for image-processing tech- 
nology to become more prevalent in 
more applications, costs are going to 
have to drop significantly from their 
present levels and systems are going 
to have to be more compact.” This 


has to happen at all levels of the 
system, from the hardware and soft- 
ware development right down to the 
rudiments of power supplies and 
packaging. re 


m@ VME64 and VSB 
w MIL Spec 


w 320 MFLOPS Performance 
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CIRCLE NO. 42 
64 DECEMBER 1992 COMPUTER DESIGN 


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CIRCLE NO. 43 


BTECHNOLOGY DIRECTIONS 


CAE/CAD TOOLS 


No agreement on best way 
to link digital and analog simulators 


Mike Donlin, Senior Editor 
he topic of mixed-signal simula- | 

T tion often causes heated debates 
among EDA vendors. Simply | 
stated, the arguments revolve | 
around which linking algorithms are | 
best—lockstep, leapfrog or back- 
plane. In all of these environments, 
digital and analog simulators per- 
form separate tasks, each simulat- | 
ing the portion of the circuit that it’s 
assigned. Usually, the faster digital 
simulator has to wait for the slower 
analog engine to perform its duties. 

Whenever one simulator needs to 
pass information to the other, the 
communication is done through a 
software interface that links the | 
two. This algorithm can be part of a 
simulation backplane that lets mul- 
tiple simulators communicate, or it 
can be achieved by a simulator-spe- 
cific algorithm that links the chosen 
simulators tightly together. 


| Backplane vs leapfrogging 


Proponents of the backplane ap- 
proach argue that having a range of 
choices for simulation tasks lets you 
select the tool that’s best for the job. 
They say that no one algorithm is 
suited to simulate the different com- 
ponents in a complex circuit, and 
that accuracy is often sacrificed for 
performance when a simulator is too 
generic. An algorithm for a switched 
capacitor filter, for example, won't | 
handle anything else, but it’s accu- 
rate because it’s tailored to simulate 
one device and is faster than Spice. 

EDA vendors such as Cadence De- 
sign Systems (San Jose, CA) and 
Mentor Graphics (Wilsonville, or) 
use the backplane method, which 
integrates digital, analog and 
mixed-signal algorithms into a ho- 
mogeneous environment. But there 
are problems with such an ap- 
proach—namely, in timing the 
events of multiple simulators to re- 
flect the real-world behavior of a 
circuit as its digital and analog com- 
ponents interact. 

“Many people who use the back- 
plane method set up a time-based 
intercommunication,” says David | 
Smith, vice-president of engineering | 
at Analogy (Beaverton, oR). “This 


means that each simulator works 
within a time slice—say, of 1 ns—to 
perform a function. That’s well and 
good, but with that approach, events 
aren’t necessarily simulated when 
they actually happen in the circuit. 
They happen plus or minus an error 
term, which makes the simulation 
efficient but lowers accuracy. If you 
make the time slice very small, ac- 
curacy goes up, but efficiency goes 
down because there’s a lot more 
event traffic on the backplane.” 
Analogy solves this problem by 


avoiding the backplane approach al- 
together and using its Calaveras al- 
gorithm to tie its analog simulator, 
Saber, to the Cadat digital simulator 
from Racal-Redac (Mahwah, NJ). 
The tools are linked together in a 
master/slave configuration, with the 
user deciding which simulator will 
assume the dominant role. The sim- 
ulators run concurrently and are 
synchronized via the Calaveras al- 
gorithm, which lets the analog sim- 
ulator go beyond a digital event and 
run at full speed. If a digital event 


LOCKSTEP SYNCHRONIZATION 


ANALOG | 


Mixed-signal algorithm comparison 


DIGITAL | 


T4 


LEAPFROG SYNCHRONIZATION 


ANALOG 


DIGITAL 


i T2 


T6 


STEP BACK AND RESTART 


GenRad’s Shado simulator uses the lockstep algorithm for synchronization of 
analog and digital simulation engines. With this approach (top), the digital engine 
is the master, the analog the slave. At time step t0, the analog engine is asked to 
simulate up to the time of the next event in the digital queue, t1. After, the digital 
engine simulates the event at t1, resulting in a new scheduled event at t2. The 
analog engine now tries to simulate up to t2, but finds an event occurring at t1 + 
a, short of t2, which will affect the digital simulator. It then stops at t1 + a and 
passes control back to the digital engine, which reschedules and simulates the 
event at t1 + a. GenRad compares this to the leapfrog algorithm (bottom), in which 
the faster digital simulator is allowed to run ahead of the analog engine. If the 
digital simulator arrives at time t4 with an event to pass to the analog simulator, 
it waits until the analog engine reaches t4 to transmit data. If the analog engine 
is at event t2 when the digital event t4 occurrs, the analog engine finds an event 
relevant to the digital engine, and the digital simulator steps back to t2 and restarts. 


66 DECEMBER 1992 COMPUTER DESIGN 


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CIRCLE NO. 73 


ETECHNOLOGY DIRECTIONS 


CAE/CAD TOOLS 


Analogy’s Saber analog simulator can use synthesized behavioral models to shorten 
simulation times. The behavioral model of a switched capacitor filter (blue line) pro- 
duced from Saber’s model synthesis runs over 250x faster than the equivalent primi- 
tive circuit representation. The model closely correlates with the actual device output 
(yellow line) over the entire operating range. 


occurs that will influence the analog 
circuitry, the analog simulator rolls 
back and resimulates. 

“This approach is different than 
some mixed-signal simulators that 
backtrack,” Analogy’s Smith ex- 


plains. “Those simulators throw out | 


the last analog values computed and 
recompute with the digital event as 
the next time step. This wastes valu- 
able cpu time because it throws out 
previously computed solutions. The 
roll-back algorithm, on the other 
hand, doesn’t throw away the infor- 
mation it’s already calculated. It 


knows, by the mathematics of calcu- | 


lating the solution at the end point, 
all the solutions along the curve 
from the previous time point. In- 
stead of throwing out the current 
solution and starting over from the 
previous event, then, it simply rolls 
back to the time where the event 
occurred and uses that value with- 
out recomputing the whole event.” 
Critics of this approach say that 
any backtracking wastes CPU time 
and is inefficient. “The leapfrog ap- 
proach is memory-intensive and ex- 
pensive in Cpu time,” says John 


Palmer, mixed-signal product man- | 


ager at GenRad (Concord, MA). 
“With that approach, the faster dig- 


ital simulator arrives at an event 
and waits for the analog simulator. 
But if the analog engine determines 
that an event relevant to the digital 
engine needs to be transmitted 
across the A-D interface, then the 
digital engine must step back and 
restart. This means that the fastest 
engine must store large amounts of 
event history, which uses a lot of 
memory, and must constantly load 
and reload data, which is expensive 
in CPU time. In general, leapfrog al- 
gorithms only offer a benefit if the 
analog and digital engines run on 
separate cpus, and even then, 
they’re very circuit-dependent.” 


Bf GenRad introduces lockstep 


GenRad’s recently released Shado 
mixed-signal simulator uses a lock- 
step algorithm to tie its digital sim- 
ulator, HISIM, with an analog simula- 
tor, Eldo, from AnacAb, a German 
company with offices in Fremont, CA. 
At any given time step, the analog 
engine is asked to simulate to the 
time of the next event in the digital 
queue. After doing so, the digital en- 
gine is free to simulate to the next 
event. If the analog simulator ar- 
rives at a solution that will affect the 
digital simulator, it passes control to 


| the digital engine, which simulates 


up to the event at which the analog 
engine stopped, using the new infor- 
mation computed by the analog sim- 
ulator. GenRad claims that this 
eliminates a lot of the inefficiency 
associated with leapfrog algorithms. 

“Td have to take issue on the effi- 
ciency question,” argues Analogy’s 
Smith. “Because with the lockstep 


| approach, the overall simulation 


speed depends on the slower of the 
two engines—namely, the analog. 
It’s true that there’s a cost for rolling 
back, but if you do a statistical anal- 
ysis, you'll find that, for many cir- 
cuits, that doesn’t happen very of- 
ten. When you do have to roll back, 


| our algorithm lets you save un- 


changed data, so the recomputation 
is reduced. I guess if your circuit 
behaves in such a way that every 
digital event affects an analog event, 
then lockstep would make sense.” 

Proponents of the backplane ap- 
proach say that, while simulation 
speed and accuracy are important, 
the real issue is flexibility and ease 
of use. “We think it’s important not 
to lock your design to any one or two 
simulators,” says James Spoto, vice- 
president of R&D at Cadence. “By 
keeping a simulator environment 
open, you can pick different levels of 
simulation and tie them together 
hierarchically, depending on the 
level of detail you need. That means 
you could use every level of simula- 
tion, from behavioral- to circuit- 
level, and tie them together through 
one user interface.” 

Regardless of the claims and 
counterclaims, however, most ven- 
dors agree that the real key to choos- 
ing a simulator is knowing what 
youre going to simulate. Each of 
these methods has drawbacks in 
speed, accuracy or ease of use—and 
each has strengths in the same 


| areas. The real winner will be the 


one best suited to your circuit. 


For more information about the technol- 
ogies, products or companies mentioned in 
this article, call or circle the appropriate 
number on the Reader Inquiry Card. 


Analogy 

(503) 626-9700 Circe 225 
Cadence Design Systems 

(408) 943-1234 Circle 226 
GenRad 

(408) 432-1000 Circle 227 
Mentor Graphics 

(800) 547-3000 Circle 228 
Racal-Redac 

(800) 526-0680 Circle 229 


68 DECEMBER 1992 COMPUTER DESIGN 


COMPASS Is ALL You NEED. | : = 


SILICON 


VERIFICATION 


ASIC Abyss EDIF Ravine 


FLOORPLAN 


LAYOUT HDL Outback 


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The path to top- most integrated top-down ASIC So chart your course today. 
down design can be solution in the industry, from first For more information, please 
anything but straight —_ concept to first silicon. Supporting circle the reader number, call 
and narrow. And even the largest and most complex (800) 433-4880, ext. 7097 or fax 
once you get off track, you can get designs that require a million gates your request to (408) 434-7977. 
into all sorts of trouble. The ASIC and more. 
wilderness is littered with good COM PA SS 
point tools that somehow fail to Simply put, we save you time. Design Automation 
provide an integrated solution. Starting with an easy-to-use 1865 Lundy Avenue 
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knows all about the rules of the comprehensive cell-based and 
road. That's because we’ve been gate array libraries. And all the Caution: ASIC design may be hazardous to your health. 
2 Design delays due to poorly integrated tools may have 
down it more than any other EDA automated tools you need to a detrimental effect on your career. COMPASS assumes 
4 i = no responsibility for those who fail to follow our path to 
company. We've developed the move on down the design road. Silicon Success. 


© 1992 COMPASS Design Automation, Inc. COMPASS and the COMPASS logo are registered trademarks of COMPASS Design Automation, Inc 


CIRCLE NO. 44 


ETECHNOLOGY DIRECTIONS 


ASICs & ASIC DESIGN TOOLS 


EDA vendors push to boost 
top-down design productivity 


Barbara Tuck, Senior Editor 


ith real technological in- | 
novation apparently stale- 


mated, suppliers of design 
automation tools are zeroing in on 
business opportunities that fall 
under the category of services. 
Vendors have discovered that it 
takes more than sophisticated 
toolsets to increase productivity 
with an HDL- and synthesis-based 
top-down design methodology. 
It also takes libraries that can 
be quickly characterized to the 
latest processes, a strategy for 
design reuse, and consulting 
services. 

When Compass Design 
Automation (San Jose, CA) re- 
cently announced the com- 
mercialization of its physical 
layout libraries of low-level 
components—the first such of- 
fering from a major EDA vendor 
that provides foundry flexibil- 
ity and support for multiple 
toolsets—Dan Skilken, world- 
wide product marketing direc- 
tor said, “Commercial librar- 
ies are a bit of a change for the 
EDA industry. We see it as a 
more complete solution, one 
that will let the industry focus 
more on productivity and 
value added.” The Compass 
Liberty Series of gate-array 
and standard-cell libraries 
and compilers for CMOS ASICs 
and AssPs for example is inte- 
grated with the Compass ASIC 
Navigator top-down design 
system. 


Bf Trend toward library sales? 


What is the company’s ratio- 

nale for going into the library 

business? “Ic designers and sup- 
pliers need more from EDA compa- 
nies than good design tools to suc- 
cessfully respond to today’s market 
pressures,” says president Dieter 
Mezger. “To keep pace with rapid 
advances in production capability 
and design complexity, they require 
a robust set of library products that 
provides a solid foundation on which 
to build new and more advanced de- 
signs. This trend toward library 


70 DECEMBER 1992 COMPUTER DESIGN 


commercialization in the 90s closely 
parallels the acceptance and prolif- 
eration of commercial CAE and CAD 
tools in the late ’70s and ’80s.” 

The Compass libraries include 
schematic descriptions, functional 
models, physical layouts, footprints, 
simulation models, and icons for 
low-level library elements. Also 
available are RAM, multiplier and 


Sierra Semiconductor uses the Compass physical layout 
libraries and compilers in the design of its DSP-based 
communications chip sets, which integrate voice, fac- 
simile and data functions. Andy Varadi, vice-president 
of R&D at Sierra (seated at left), discusses the compiled 
datapath layout (on screen) for the company’s new 
V.32 modem chip with design team members Neil 
Becker and James Tan. “Using Compass digital libraries 
enables us to spend more time on what we’re unique 
at—analog and mixed-signal design,” Varadi says. 


datapath compilers. After a foundry 
is selected, Compass uses automated 
tools and techniques to generate tim- 
ing models and layout for a specific 
set of design rules. On average, ac- 
cording to Compass, the customiza- 
tion of a subset of the full Liberty 
Series takes six to ten weeks. As part 
of its customization services, simula- 
tion models are generated for most 
popular simulators. Both VHDL and 
Verilog are supported. 


Will semiconductor vendors em- 
brace the concept of physical layout 
libraries being sold by EDA vendors? 
For fabless semiconductor vendors 
such as Sierra Semiconductor (San 
Jose, CA), vice-president of R&D Andy 
Varadi says that the Compass li- 
brary service is useful. “Using Com- 
pass digital libraries lets us spend 
more time on what we’re unique 
at—analog and mixed-signal de- 
sign. We can differentiate ourselves 
in a new dimension,” he says. 

Although Sierra’s been using 
Compass libraries extensively, it’s 
been doing so on a contractual basis 
rather than purchasing the libraries 
outright. Now that Sierra is 
buying Compass general-pur- 
pose libraries that can be tar- 
geted to any silicon vendor’s 
process, Varadi says that “We 
have a greater degree of free- 
dom. We didn’t have foundry 
flexibility before. Now we can 
change process or vendor, and 
we can move products from 
one process to another by re- 
characterizing and resimulat- 
ing.” 

For semiconductor compa- 
nies with in-house fabs but not 
much asic technology, the 
Compass libraries may pro- 
vide an opportunity to get into 
the ASIC and ASSP businesses. 
For others, the libraries could 
augment current offerings or 
save characterization time. Li- 
brary users can also leverage 
their investments through de- 
sign reuse. 


I Design reuse a goal 


The methodology, tools and re- 
lationships enabling smart 
reuse of designs is the focus of 
anew business segment called 
DesignWare at Synopsys 
(Mountain View, CA). Intel- 
ligent design reuse and the 
consequent leveraging of in- 
dustrial intellectual property will 
yield the productivity required to re- 
main competitive, according to Syn- 
opsys, which claims that previous 
strategies for design reuse haven't 
taken advantage of synthesis as an 
enabling technology and VHDL as the 
worldwide language standard. 
“VHDL gives the practical promise of 
being the standard for capturing and 
describing everything,” says Aart de 
Geus, Synopsys’ senior vice-presi- 


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IDA instant D 


ETECHNOLOGY DIRECTIONS 


dent and chairman of the board. 

To be available by year’s end, the 
first two design-reuse products from 
the Synopsys DesignWare division 
are Synthetic Designs, consisting of 
off-the-shelf synthesizable compo- 
nent libraries, and software called 
DesignWare Developer for designers 
wanting to capture their own syn- 
thesizable and reusable modules. 
Both are integrated with the com- 
pany’s Version 3.0 high-level design 
tools—vHDL System Simulator, De- 
sign Compiler and Test Compiler. 

Synthetic Designs are technology- 


independent, parameterized librar- 
ies of commonly used functions such 
as ALUs and multipliers that have 
been preverified with the Synopsys 
VHDL simulator. These functions can 
be instantiated in a VHDL or Verilog 
description or inferred from HDL op- 
erators. The user configures the 
Synthetic Design library component 
for a particular system design by 
supplying specific parameters and 
compiling to a target technology. 
The Synopsys synthesizer then opti- 
mizes for the context of the sur- 


72 DECEMBER 1992 COMPUTER DESIGN 


The Synopsys DesignWare synthesis-based design-reuse strategy permits the reuse of 
existing designs through automatic selection based on design constraints or by manu- 
al selection of a component through a menu-driven interface. In this photo, the menu 
for selecting a Synthetic Designs library family is shown (top left), and the desired 
component within that library family may be selected (bottom left). The existing de- 
sign is shown with multipliers (yellow), subtracters (pink) and adders (red). 


ASICs & ASIC DESIGN TOOLS 


rounding system, choosing appro- 
priate drives and loads. 

If you want to build your own 
inventory of reusable modules tai- 
lored to your particular design re- 
quirements, you can use the new 
DesignWare Developer to create, 
manage and protect your propri- 
etary design data. The software 
gives you a way to key and encrypt 
designs that can then be distributed 
to users while intellectual property 
is safeguarded. 

Harvey Jones, Synopsys presi- 
dent says, “We expect third parties 


and end customers to use Design- 
Ware Developer to share their intel- 
lectual property with their leading 
customers and with the general 


(Munich, Germany) to provide 
through the DesignWare program a 
wide range of system-level models. 
Also, Synopsys, Texas Instruments 
(Dallas, Tx) and Comdisco Systems 
(Foster City, cA) will be focusing on 
optimizing design productivity us- 
ing core DsP architectures. 


B Hands-on training 


To ensure productivity for those 
adopting VHDL-driven top-down de- 
sign, Mentor Graphics (Wilsonville, 
OR) has opened several design cen- 
ters in the United States, Japan and 
Europe and has teamed with leading 
ASIC and FPGA vendors, as well as 
workstation vendor Sun Microsys- 
tems, in a worldwide training pro- 
gram called SmartStart. Mentor’s 
vice-president of corporate market- 
ing, David Chen, says, “In the past, 
engineers have been reluctant to 
transition to a top-down methodol- 
ogy because the industry didn’t offer 
a solution with the level of integra- 
tion, support or training necessary 
to make the change. The SmartStart 
program offers a complete solution 
consisting of software, hardware, 
silicon fabrication, and support ser- 
vices to ensure that customers meet 


| time-to-market goals.” 


During SmartStart training, you 
get the hands-on experience of tak- 
ing a design from VHDL to layout. 
Fujitsu, st Logic, Mitsubishi, visi 
Technology, and Xilinx have teamed 
with Mentor to provide a fully qual- 
ified and endorsed design flow 
within Mentor’s Version 8.0 design 
environment. Each of these vendors 
is offering design kits based on Men- 
tor’s Advanced Modeling Process 
(AMP) ASIC modeling technology to 
support the company’s recently an- 
nounced vVHDL-based, fully inte- 
grated, top-down toolset called De- 
sign Solver. Mentor’s System-1076 


| VHDL simulator will fully comply 
| with the IEEE 1076 specification by 


year’s end. cd 


marketplace. As our customers im- 
plement increasingly complex sys- 
tems in silicon, the ability to reuse 
design data will provide the reduc- 
tion in design time required to re- 
main competitive.” 

To help you decide on the appro- 
priate system architecture to target, 


| Synopsys has entered into a part- 
| nership with Compiled Designs 


For more information about the technol- 
ogies, products or companies mentioned in 
this article, call or circle the appropriate 
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for the memories... 


At this time, we wish to extend our good wishes 
for the season and a happy and a healthy New Year, 
on a personal as well asa business level. You — 
our readers and advertisers — our friends — 
helped make 1992 a spectacular and memorable 
year for all of us at Computer Design 

and Military & Aerospace Electronics. 

Thanks — and best wishes for a terrific, 
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Militar y&Aerospace COMPUTER Technology 
Bist Asicienic8. siRurHRRs-DONN Nevsttivs Cesc DESIGN 


PENNWELL PUBLISHING COMPANY * ONE TECHNOLOGY PARK DRIVE, WESTFORD, MA, 01886 * 508-692-0700 * FAX 508-692-7780 


CIRCLE NO. 46 


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CIRCLE NO. 47 


FPGA vendors turn 


their attention to tools 


In the face of stiff 
competition, FPGA 
vendors are enhanc- 
ing proprietary tools, 
enlisting third-party 
support, adding text- 
based entry methods, 
and backing 
standards. 


fe ler GemPrree Sent Tee Berar etme tee 


Barbara Tuck, Senior Editor 


W.. FPGAs such hot items, 


silicon vendors have had a cap- 
tive audience. In concentrating 
on silicon, however, FPGA ven- 
dors haven’t always delivered 
toolsets that were easy to use or 
boasted good results. But as 
more and more vendors enter the marketplace, a competitor with tools that 
fail to route a part or whose entry methods don’t include VHDL is at an ever 
greater disadvantage. As a result, FPGA vendors are finally focusing on 
creating solutions for users. 

To satisfy the demands of electrical designers such as Fred Rakvica at 
Kodak (Rochester, Ny) for interactive place-and-route software, Actel 
(Sunnyvale, CA) just announced its Action Logic System (ALS) Release 2.2. 
With interactive placement and incremental place-and-route, ALS 2.2 will 
be available next quarter for X-Windows-based workstations. Rakvica, 
who'll be glad to finally have some control over placement, is using nine 
Actel 1280 FPGAs in a 30,000-gate project, an enhancement for Kodak’s photo 
cD program. 


B interactive placement 


Although Actel has always stressed automatic place-and-route as the 
strength of its design system, director of marketing Andy Haines acknowl- 
edges that the extra knowledge a seasoned FPGA designer such as Rakvica 
has can be important in pushing performance. “With ALS 2.2,” he explains, 
“users will be able to select the exact degree of control they’d like to have 
over their FPGA designs.” 

The interactive placement feature lets you manually fine tune the results 
of automatic place-and-route by viewing, moving and editing the location 
of Actel logic modules; to do so you use ALS 2.2’s graphical interface with 
icon commands. You can also rely on the automatic features of the software 
to optimize a design incrementally, without disrupting the placement or 
disturbing timing optimization. On top of all this, ALS 2.2 offers improved 
macro modeling for up to 25x faster simulation speeds. 

Newcomer Concurrent Logic (Sunnyvale, CA) wooed away Actel user Tom 
Minnis, senior project engineer at Larse Corp (Santa Clara, CA), before Actel 
introduced its improved toolset. (Larse manufactures communications pro- 
ducts.) Though Minnis’ FPGA choice was ultimately based on silicon, (accord- 
ing to him, Concurrent’s CLi6000 Series is the only FPGA with the freedom 


COMPUTER DESIGN 


Actel’s Action Logic 
System 2.2 uses a 
Motif-compatible X- 
Windows interface 
and features stan- 
dard X-Windows 
menus, a list box 
(upper righthand 
text box) that 
shows all “in- 
stance” names ina 
flattened versus a 
hierarchical mode, a 
context window 
(lower righthand 
window) that 
shows the current 
zoom area on the 
full chip layout, and 
a main viewing 
area that shows 
three windows con- 
taining different 
zoom perspectives 
of the same chip 
layout. 


DECEMBER 1992 75 


ETECHNOLOGY FOCUS: FPGA TOOLS 


to distribute multiple clocks without 
introducing skew), design tools, may 
also have influenced the change in 
vendor. “Concurrent has a beautiful 
manual place-and-route program 
with a very good interactive editor,” 
says Minnis. “Up until now, Actel’s 
software has been push-button.” 

About two months ago Concur- 
rent Logic also made an incremental 
design change, adding a feature to 
its pc-based CDS2100 Development 
System, which combines design en- 
try from Viewlogic (Marl- 
borough, MA) with propri- 
etary back-end tools. 
With the new feature, you 
can change a schematic 
that’s been completely or 
partially laid out, and im- 
plement the change in 
the layout without dis- 
turbing the existing 
placements and routes. 
By year’s end, Concur- 
rent will offer a Sun 
workstation interface, 
and by early next year 
CLi6000 designers will 
have the option of using 
Verilog and Synopsys 
(Mountain View, CA) syn- 
thesis. 

Not wanting to be 
locked into a single FPGA 
vendor, especially one as 
new to the field as Concur- 
rent Logic, Larse is also 
buying silicon and tools from Xilinx 
(San Jose, CA). But Minnis is no 
booster of Xilinx place-and-route 
tools. “It’s really tricky to use Xil- 
inx’s interactive editor to move stuff 
around,” he believes. 


Bl Specifying timing up front 
Xilinx began shipping a tool two 
months ago it says will significantly 
reduce the need to manually parti- 
tion and route critical portions of 
logic cell array (LCA) designs, elimi- 
nating three to five design iterations 
in the process. As part of Xilinx’s 
latest version of its XACT 4000 de- 
velopment system, the new XACT- 
Performance tool lets you enter your 
register transfer requirements 
(clock-to-setup), /o transfer require- 
ments (pad-to-setup and clock-to- 
output), and combinatorial logic re- 
quirements (pad-to-pad) in your 
schematics. The tool will inform you 
early if performance requirements 
are unrealistic for the design. 

An early user of xact-Perform- 
ance, consultant Rocky Awalt, pres- 
ident of Highgate Design (Saratoga, 


76 DECEMBER 1992 COMPUTER DESIGN 


CA), relied on the new Xilinx soft- 
ware, which he refers to as deadline 
timing, to show engineers at client 
Boeing Aircraft (Renton, wA) why 
one of their 4005 LCAs wasn’t work- 
ing properly. Boeing designers are 
using dozens of Xilinx FPGAs on a 777 
aircraft. “Before xact-Performance 
was available,” says Awalt, “Xilinx 
users complained about having to do 
a detailed analysis after compiling a 
design to determine whether or not 
the desired result had been 


A Concurrent Logic FPGA user, senior project engineer Tom Minnis 
of Larse Corp uses the Concurrent interactive editor, Interact, to 
place and interconnect functional cells in a CLi6000 FPGA design 
destined for a T1 transmission product. “Concurrent’s software 
shows you all the possibilities,” reports Minnis. 


achieved. The new software is quite 
powerful and will meet your timing 
specifications.” 

About FPGA tools in general, and 
Xilinx tools in particular, Awalt says 
the routing delays and learning curve 
involved make it “nearly an oxymoron 
to speak about ease of use and perfor- 
mance at the same time. But there’s 
no such thing as a slow Xilinx LCA. 
There are just slow engineers.” 

Senior design engineer Gene 
Jones at Universal Computing (San 
Diego, CA), a maker of bus boards 
and design consultants doing cus- 
tomer-driven designs, would proba- 
bly disagree with Awalt. Jones de- 
signed a Xilinx 3090 LCA into a 
multiprocessor board for the VMEbus 
and had to take it out and replace it 
with a QuickLogic (Santa Clara, CA) 
paAsic because the Xilinx part 
wouldn’t run at 20 MHz. “After you 
route a Xilinx part,” explains Jones, 
“you can have internal delays of 
hundreds of nanoseconds. I don’t 
have a person who can be a master 
of Xilinx tools. With QuickLogic, I 
don’t need an expert.” 


Jones says he gets both perfor- 
mance and ease of use with Quick- 
Logic. “And with QuickLogic,” he 
adds, “there’s the predictability fac- 
tor. I can understand and predict 
what a part’s going to do, whereas 
with Xilinx, I don’t know until after 
place-and-route.” Just about the 
time Jones was giving up on the 
Xilinx 3090, Xilinx was introducing 
its 3100 family, which is pin- and 
software-compatible with 3000 
parts and yet is up to twice as fast. 

QuickLogic has sought 
to expand its customer 
base by enlisting third- 
party support. For the 
broad installed base of 
ABEL users, now number- 
ing over 30,000 PLD and 
FPGA designers world- 
wide, QuickLogic has 
partnered with Data vo 
(Redmond, WA), which de- 
veloped a device fitter for 
the pASIC 1 family. For 
designers wanting to 
stick with device-inde- 
pendent tools, Quick- 
Logic has shared technol- 
ogy with third-party 
NeocapD (Boulder, co), so 
that NeocaD’s FPGA Foun- 
dry can support the 
pAsic 1 family. FPGA 
Foundry also supports 
Xilinx devices. 

A heavy user of FPGAs, 
Derek Rowe, CEO and chief engineer 
at Defence Products (Lower King- 
swoo, Surrey, U.K.), prefers to use 
FPGA Foundry rather than Xilinx 
tools to place and route the LCAs he 
designs into aircraft navigation sys- 
tems. “NeocaD is an order of magni- 
tude faster, and it’s right every 
time,” says Rowe, who’s now await- 
ing the second release of FPGA Foun- 
dry, which will include as an option 
a timing-driven tool called Timing 
Wizard. “This new tool will remove 
the need for manual iteration to 
achieve a maximum delay for a de- 
sign,” says Rowe, explaining that up 
until now designers have had to be 
conservative on the chip’s behalf be- 
cause of the unpredictability of tim- 
ing delays. 


| Partitioning options open up 

NeocaD announced a few weeks ago 
that the second release of its FPGA 
Foundry would also include an op- 
tional timing-driven tool called 
Prism, which provides automatic 
post-mapped partitioning of logic 
functions into multiple FPGAs. Un- 


Selecting FPGA design tools 


Becouce of the 


advantages offered 
by programmable 
devices, many engi- 
neers are finding 
themselves design- 
ing their first FPGAS. 
As experienced us- 
ers will confirm, 
having the right tools is just as critical to 
this process as selecting the right device. 

The right tools offer a minimum learn- 
ing curve, shorter design cycle, maxi- 
mum chip utilization and performance, 
and support for the device that's best 
suited to the design. The following 
guidelines will help FPGA designers select 
the proper tools for their needs. 


B What makes a good toolset? 

1) A good toolset should support the ex- 
isting CAE design environment. You 
should be able to use your existing cap- 
ture and simulation tools. 


2) It should be complete. A minimum 

toolset should include: 

¢ Entry from all popular design 
methodologies (Palasm/aseL, sche- 
matic capture, VHDL), as well as transla- 
tors from industry standards such as 
EDIF and LPM. 

¢ Mappers or fitters to convert your orig- 
inal design elements into the logic ele- - 
ments available in the selected FPGA. 

* Device-specific optimization to provide 
efficient utilization of the logic within 
the FPGA without requiring you to man- 
ually perform device-specific optimiza- 
tion during design capture. 

¢ Automatic placement and routing. 

¢ A graphical editor with online design 
rule checking that can be used for pre- 
placing and routing critical signals, or 
debugging the design after the auto- 
matic tools have finished. 

¢ Timing analysis, with the ability to 
compare the completed design 
against user-specified requirements 
and report back on potential problems. 

e Automatic back-annotation of timing 
delays to the simulator of choice. 


3) A toolset must deliver shorter time-to- 

market. To make this a reality, the best 

FPGA design tools: 

¢ Keep the FPGA design cycle to the 
fewest iterations possible. This can be 
achieved using sophisticated algo- 


rithms which converge on the best so- 
lution, and a rules-driven approach 
where requirements are set up front 
to reduce the amount of cleanup re- 
quired in the end. 

¢ Provide the shortest time per iteration. 
This can be done by using fast-execut- 
ing algorithms, as well as the support 
of an incremental design capability 
where small changes don’t require a 
total relayout of the design. 


4) The ability to optimize the perfor- 
mance and utilization of existing devices 
is essential. It's vital that the toolset pro- 
vides efficient optimization routines to 
best fit a design into the specific archi- 
tecture. Utilization and performance re- 
sults can vary considerably from fitter to 
fitter. Fortunately, the results are quantifia- 
ble, which lets you make comparisons 
easily through benchmarks. 


5) The toolset should provide complete 

control over itself and results. Auto- 

mated solutions will only give satisfac- 

tory results if you can truly direct the 

tools. You should be able to: 

¢ Specify preferences up front, with the 
tools adhering to these rules. Prefer- 
ences include physical constraints such 
as pin-outs and floorplanning, and tim- 
ing requirements such as clock fre- 
quencies, skew and path delays. 

¢ Prioritize trade-offs. Tool developers 
constantly have to make decisions 
such as whether they need algorithm 
speed vs sophistication, with more 
complex algorithms requiring more 
time to execute. 


6) It should have timing-driven capabili- 
ties. By specifying exact timing require- 
ments up front—frequency and path 
delays, and not just routing priority or 
critical versus non-critical—timing prob- 
lems can be eliminated before they even 
occur. As a result, timing-driven tools 
shorten the design cycle while providing 
significantly faster clock speeds. If for 
some reason the tools can’t meet the re- 
quirements automatically, they can pin- 
point exactly where the timing problem 
occurs, as opposed to the search-and- 
find tactics otherwise required. 


7) Make designing FPGAS simple. To do 
this the tools must: 
Let you think in terms of your original 


design methodology. An asic designer 
using an FPGA for prototyping, for ex- 
ample, shouldn't be required to de- 
sign as if the FPGA and not the Asic 
was the primary focus. 

¢ Not require you to become an expert on 
the chip architecture to take full advan- 
tage of the device. This can be done us- 
ing a combination of powerful 
automatic tools to handle all but the 
most difficult or unusual design prob- 
lems, while letting you set requirements 
by specifying the desired result instead 
of detailing a specific implementation 
methodology (such as stating that the 
maximum path delay between registers 
isn't to exceed 20 ns, as opposed to 
“place the design in these logic blocks, 
route the nets in this order, and use 
these specific routing resources”). 


8) Device independence is becoming in- 
creasingly important as FPGA vendors 
continue to enter the market and the 
tool must support this. Since each FPGA 
architecture has unique advantages and 
disadvantages, this trend is good for the 
user. You shouldn't have to buy and 
learn multiple sets of tools, however, to 
take advantage of newer devices which 
better fit your design requirements. In 
addition, tools should support the abil- 
ity to retarget existing designs. 


9) Support of a technology-transparent 

design methodology is also important. 

This involves the ability to perform de- 

sign capture and functional verification 

independent of the final implementa- 

tion technology (whether it be pcs, FPGA 

or gate array). The tools should: 

¢ Provide the ability to capture a design 
using generic libraries and attribute 
files, freeing designers from being 
locked into a specific architecture. 

¢ Handle device-specific constraints and 
rules through files separate from the 
schematic itself. If the information ex- 
ists in the schematic, then the sche- 
matic itself will have to change to 
target a different device. 

¢ Support the ability to easily transition 
from one FPGA architecture to another, 
as well as between FPGAS and ASICS. 


10) Finally, the toolset must run on pop- 
ular platforms, such as Pcs and engineer- 
ing workstations, and support standards 
such as EDIF and LPM. 


Bob Anastasi, senior vice-president, NeoCAD, Boulder, CO 


COMPUTER DESIGN DECEMBER 1992 77 


Before you link up with a pro 


©1992 Altera Corporation. MAX, MAX+PLUS and FLEX are trademarks of Altera Corporation. 


grammable e logic company, 
check our strengths. 


At Altera we continually ask, “What more can we do to become 
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Check our lower prices. We’re committed to providing the most 
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Connect with Altera today. Call 
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CIRCLE NO. 48 


BETECHNOLOGY FOCUS: FPGA TOOLS 


like the traditional approach of di- 
viding the design at the schematic 
capture level, Prism partitions after 
the technology-mapping process, 
taking into account the timing re- 
quirements and technology-specific 
characteristics of the targeted FPGA 
architecture. 

Quickturn Systems (Mountain 
View, CA) has also announced that it 
will begin shipping an FPGA par- 
titioning tool this month based on 
technology developed for its hard- 
ware emulation systems. Quick- 
turn’s Automatic Design Partitioner 
divides large designs into multiple 
partitions based on user-specified 
gate and pin-count parameters. 
Quickturn’s European counterpart, 
ASIC emulation company Inca 
(Ascot, Berkshire, U.K. and Camp- 
bell, CA), has been leveraging par- 
titioning technology developed for 
its Virtual ASIC emulation system by 
selling a stand-alone partitioning 
tool since last summer. Inca’s Con- 
cept Silicon compiles and partitions 
a complex digital design into hard- 
ware containing multiple FPGAs from 
different manufacturers. 

FPGA vendors have also had to rec- 
ognize that users are beginning to 


couple a hardware description lan- 
guage (HDL) synthesis design meth- 
odology with FPGA technology. Speci- 
fying functionality, area and 
performance goals at the register 
transfer level, theyre looking to syn- 
thesis tools to generate the optimal 
implementation. But technology 
translation and optimization for 
FPGA architectures, which vary sig- 
nificantly from vendor to vendor, 
present tremendous challenges to 
synthesis tools, particularly tools 
such as those from Synopsys, which 
are geared to synthesizing the fine- 
grained architectures of gate arrays. 


Bf synthesis challenged by timing 


Commenting on these challenges, 
Jerry Rau, marketing manager at 
Synopsys, says, “One of them is crit- 
ical-path timing. To give predictable 
results, placement and routing tools 
must know which nets are most crit- 
ical, and they also need to know the 
delay slack available on each net. 
Logic synthesis tools can easily iden- 
tify the delay slack, but to do so 
accurately requires predictable pre- 
layout wire load estimates. This 
means that a vicious circle exists 
today; both layout and synthesis 


Exemplar Logic’s CORE Solution offers vendor-independent design synthesis and tech- 
nology-specific optimization for FPGAs. This screen shot shows (clockwise from the 
upper left): CORE’s user interface, VHDL, background schematics, CORE’s Design Sum- 
mary Report, and CORE’s run-time window. Exemplar offers a growing range of de- 
sign kits, all leveraging industry or de facto standards and covering Boolean, PLD, 
Verilog, and VHDL entry. 


80 DECEMBER 1992 COMPUTER DESIGN 


tools are waiting for timing data 
that the other can provide only when 
the process is complete.” 

Rau sees two viable solutions to 
this problem emerging. “One solu- 
tion,” he says, “calls for FPGA vendors 
to use hard macros—large func- 
tional blocks, such as adders and 
multipliers, which are pre-charac- 
terized for speed and area. A logic 
synthesis tool such as Synopsys’ De- 
sign Compiler can automatically 
evaluate different implementations 
of a particular function and choose 
the one that best meets overall de- 
sign goals. A second solution is con- 
straint-driven layout, which re- 
quires cooperation between FPGA 
and EDA vendors. Logic synthesis 
can provide rich detail about the 
criticality of every delay path. This 
information, when passed to place- 
and-route tools, can be of great help 
in fulfilling the designer’s intent.” 

Some FPGAs have a finer granular- 
ity than others, making them better 
candidates for Synopsys synthesis. 
The Crosspoint Solutions (Santa 
Clara, CA) CP20K FpaGas, for exam- 
ple, are ideal for Synopsys synthesis 
because they have a fine-grained, 
gate-array-like architecture. Vacit 
Arat, director of marketing for Cross- 
point, says, “Our very first customer 
fine-tuned his design for performance 
using Synopsys tools. It was 100-per- 
cent automatically placed and routed 
on our 4,200 FPGA, the CP20420, with 
no manual intervention, and it ran 
at 50 MHz.” Crosspoint also offers a 
Design Kit for Mentor Graphics’ 
(Wilsonville, oR) AutoLogic 8.0 logic 
synthesis tool. 

Unlike the Crosspoint FPGA, the 
Xilinx LCA’s architecture presented a 
real challenge for Synopsys synthe- 
sis until finally Xilinx and Synopsys 
together developed xsI, or the Xil- 
inx/Synopsys Interface. The xsi li- 
brary correlates to the multiple-in- 
put, look-up-table (LUT) architecture 
upon which Xilinx LCAs are based. 
With more than 65,000 functions 
needing representation, mapping 
logic functions as LUTs is more effec- 
tive than mapping them as primi- 
tive gates. “Xilinx xsI provides de- 
signers access to the familiar VHDL 
and Verilog/HDL languages,” says 
Jacob Jacobsson, the company’s 
vice-president of development sys- 
tem products, “while optimizing the 
design for the Xilinx FPGA architec- 
ture. It may have taken longer to 
develop the library for an optimized 
solution, but for the user, it’s worth 
the wait.” 


Ss 


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% TEXAS 
INSTRUMENTS 


BTECHNOLOGY FOCUS: FPGA TOOLS 


The wait for a Xilinx/Synopsys so- 
lution may not be over yet, though, 
for senior electronic design engineer 
Brian Box at Lockheed Sanders 
(Nashua, NH), where engineers have 
done upward of 400 distinct designs 
with Xilinx FPGAs. While Box says 
his hopes are very high that xsI will 
be usable for mainstream projects at 
his company, at present its use is 
limited to research. For engineers to 
use XSI on the Xilinx parts they de- 
sign into electronic warfare sys- 
tems, area and timing optimization 
have to be enhanced. According to 
Box, “Synopsys has to have the con- 
trol to feed timing constraints to the 
Xilinx place-and-route tools. The 


tion and chip implementation.” 


| FPGA-specific synthesis 


When hardware engineer Van Oler, 
working at SpaceLabs Medical (Red- 
mond, WA), made a simple logic 
change to an LCA in a patient moni- 
tor he was working on, he found that 
Xilinx tools wouldn't reroute it, so he 
resorted to Exemplar Logic’s (Berke- 
ley, CA) FPGA-specific synthesis. “We 
sent Exemplar the Xilinx netlist 
file,” he says, “and they synthesized 
it and reduced the number of mac- 
rocells, freeing up some routing re- 
sources so the Xilinx tools could 
route the part.” SpaceLabs has since 
purchased Exemplar’s Complete 


LPM design flow 


HIGH-LEVEL 
SYNTHESIS 


SCHEMATIC 
EDITOR 


LPM NETLIST 
(CAN BE MULTIPLE FILES) 


TECHNOLOGY 
FITTER 
SILICON 


BEHAVIORAL 
DESCRIPTION 


LOW-LEVEL 
SYNTHESIS 


This diagram illustrates the basic tool structure that will implement the Library of Par- 
ameterized Modules (LPM) standard. The master netlist file is an EDIF netlist that uses 
only the components defined in the LPM specification. The technology fitter maps a 
logical netlist onto a physical implementation, including placement and routing. 


biggest achievement of xsI so far is 
that it gives you the ability to in- 
stantiate hard macros and so take 
advantage of the fast carry logic in- 
side the cLBs [configurable logic 
blocks] of Xilinx 4000 FPGAs.” 

Box recently began using VHDL. If 
and when xs!I is ready for main- 
stream use at Lockheed Sanders, he 
expects it will knock two weeks off a 
three-week FPGA design cycle. (This 
three-week period doesn’t include 
VHDL specification time.) “Today,” 
Box adds, “I have a person sitting in 
between the VHDL code and the com- 
pleted chip. We lose two weeks actu- 
ally constructing the chip, instead of 
letting a synthesis tool do it. xsi will 
give us a link between VHDL simula- 


82 DECEMBER 1992 COMPUTER DESIGN 


Optimization/Retargeting Environ- 
ment (CORE) Solution, which runs 
on UNIX- and MS-Dos-based operating 
systems. 

After trying to use an interface to 
Synopsys from Altera (San Jose, CA), 
Brent Meyer, a senior member of the 
technical staff at Sandia Labs (AI- 
buquerque, NM), says that, if handed 
a blank check by management, he 
too would purchase Exemplar’s CORE 
Solution synthesis, which now sup- 
ports MAX 5000 and 7000 devices. 
“The Altera library that runs on Syn- 
opsys has no timing information,” 
complains Meyer, who’s using a sin- 
gle MAx 5000 part as a memory in- 
terface in a system for arms control 
verification. “I had no control with 


VHDL. I couldn’t do gate-level simula- 
tion, only behavioral simulation.” 

Meyer was concerned because the 
finished design had to match the 
original source code he had brought 
to his customer. For timing prob- 
lems that showed up after Altera 
reoptimized the design, Meyer could 
either go back to the VHDL code, re- 
write constraints and resynthesize 
with Synopsys, or he could rewrite 
the VHDL code at a lower level. 

How long was Meyer’s design cycle 
for the single Altera MAX part? A 
month, he says, from the day he had 
his VHDL code ready for his customer 
to the day he had his timing problems 
resolved. In the meantime, he sent the 
project as a test file to Exemplar. “I 
received a report back within three 
days. Although I didn’t get the entire 
design back, it looked as if the timing 
would be okay. On top of that, Exem- 
plar had fitted the design into a 
smaller part,” reports Meyer. 

The Exemplar approach to syn- 
thesizing Altera parts involves de- 
velopment of a compiler module op- 
timized for the Altera architecture, 
as well as special libraries for the 
MAX 5000 and 7000 parts, with tim- 
ing information built in. “Exemplar 
synthesis produces something we 
don’t really have to resynthesize,” 
says Craig Lytle, applications 
manager at Altera, “maybe just 
tweak a little. It produces code that 
maps almost directly to our logic.” 
Exemplar outputs an AHDL file, 
which is then read into Altera’s 
MAX+Plus II toolset. Altera reports 
that it’s developing the capability to 
accept directly both vHDL and 
Verilog into its compiler, and it ex- 
pects that early next year MAX+Plus 
II will be able to produce VHDL-for- 
matted output files and, by the end 
of the year, Verilog-formatted out- 
put files, with or without timing an- 
notation. At present, Altera users 
are limited to an EDIF-formatted file. 


Bf standards on the way 


As part of the effort to create a solu- 
tion rather than a nightmare for 
users, programmable logic silicon 
and software vendors have been try- 
ing to ease the PLD and FPGA design 
tool dilemma by establishing stan- 
dards through consortiums. The 
founding and supporting members 
of one such consortium have estab- 
lished a technical standard for logic 
design called the Library of Parame- 
terized Modules (LPM), a generic, 
technology-independent set of logic 
primitives to be embedded in EDIF so 


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BTECHNOLOGY FOCUS: FPGA TOOLS 


that a netlist can be created in a 
standard way. Active participants in 
the pm effort include Actel, AT&T, 
Data vo, Exemplar Logic, Mentor 
Graphics, MINC, Neocap, Viewlogic, 
and Xilinx. 

The objective of LPM is to permit 
efficient access to unique architec- 
tures, such as those found in FPGAs. 
This access is to be provided through 
synthesis tools and other design en- 


try systems. The LPM standard lets 
any logic synthesis program that 
generates LPM map a design effi- 
ciently onto any FPGA having a fitter 
that accepts the LPM standard. 

The main purpose of a second con- 
sortium, called PREP for Program- 
mable Electronic Performance, is to 
develop standard benchmarks for 
FPGAS and PLDs. As part of this effort, 
PREP’s Working Group 2 is concerned 


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84 DECEMBER 1992 COMPUTER DESIGN 


with establishing a design entry 
standard for consistency in bench- 
marking. PREP president Stan Baker 
says, “PREP is starting its standard- 
izing efforts at the ground level, 
based on what users say they need.” 

Working Group 2 chairman Al 
Graf of Cypress Semiconductor (San 
Jose, CA) expects that a standard 
VHDL behavioral design capture 
methodology will soon be proposed 
for FPGAS and PLDs. PREP may also 
sponsor a working group committed 
to standardizing synthesis bench- 
marking tools. Companies partici- 
pating in PREP include Actel, Ad- 
vanced Micro Devices, Altera, AT&T, 
Cypress Semiconductor, Data Vo, 
Gould Ami, Intel, Lattice Semicon- 
ductor, MINC, QuickLogic, Texas In- 
struments, and Xilinx. 

Until a standard is available, 
MINC (Colorado Springs, CO), which 
offers its own PLDesigner-xL family 
of synthesis tools for PLDs and FPGAs, 
is offering a free toolkit to facilitate 
benchmark comparisons of synthe- 
sis offerings. Given a set of input 
parameters, the MINC utility pro- 
duces identical designs across all 
output formats, so you can fairly and 
accurately compare the capabilities 
of the PLD and FPGA synthesis tools 
on the market. a 


For more information about the techn- 
ologies, products or companies mentioned 
in this article, call or circle the appropriate 
number on the Reader Inquiry Card. 


Actel 

(408) 739-1010 Circle 233 
Altera 

(408) 894-7000 Circle 234 
Concurrent Logic 

(408) 522-8718 Circle 235 
Crosspoint Solutions 

(408) 988-1584 Circle 236 
Data I/O 

(800) 332-8246 Circle 237 
Exemplar Logic 

(510) 849-0937 Circle 238 
IncCA 

(408) 986-8800 Circle 239 
Mentor Graphics 

(503) 685-7000 Circle 240 
MINC 

(719) 590-1155 Circle 241 
NeoCAD 

(303) 442-9121 Circle 242 
PREP 

(408) 356-2169 Circle 243 
QuickLogic 

(408) 987-2007 Circle 244 
Quickturn Systems 

(415) 967-3300 Circle 245 
Synopsys 

(415) 962-5000 . Circle 246 
Viewlogic 

(508) 480-0881 Circle 247 
Xilinx 

(800) 255-7778 . Circle 248 


GUIs move OSs 


toward object orientation 


Computer graphics, 
originally meant to 
display data, is now 
the way users interact 
with systems. A new 
generation of operat- 
ing systems with fully 
integrated GUIs is 
meeting the demands 
of those who want to 
work with their sys- 
tems in a real-world 
environment of ob- 
jects and actions. 


Tom Williams, Senior Editor 


[. it’s true that the eyes are the windows to the soul, then graphical user 
interfaces (GUIs) are the windows to the operating system. We're in transi- 
tion from one generation of operating systems to the next, and the latter 
will have fully integrated Guis. Not only will these GuIs let you work more 
easily with the system, but they'll also define the functionality of the system 
and enforce programming discipline through application programming in- 
terfaces. 

Today’s GUIs, in fact, are having an even more profound effect on the 
community of users and software developers. Representing applications and 
utilities as little telephones and trash cans promotes the idea that we can 
manipulate our systems in terms of these objects. If you can drag and drop 
a file into a trash can, why can’t you hook an incoming data stream to a 
meter or strip chart? In some cases you can do this simply—and in more 
cases if you’re willing to write some code to run behind the graphic objects. 

These expectations have let GUIs push us steadily toward a more object- 
oriented environment, both for application development and user interac- 
tion with the system. In realtime and embedded systems that require a user 
interface, operating systems (OSs) such as Windows NT by Microsoft (Red- 
mond, WA), OS-2 from 1BM (White Plains, Ny), Nextstep from Next Next? 
Computer (Redwood City, cA), and even the ikMx realtime operating system 
for Windows from Intel (Santa Clara, CA) are including GUIs or direct support 
for GUIs as an integral part of the product. 

This is in contrast to other major operating systems, such as DOS and 
UNIX, which are about 11 and 15 years old respectively. The main GUIs 
associated with these systems, MS-Windows 3.1 and X-Windows, were 
essentially bolted on to the underlying oss. They have greatly increased the 
functionality, ease of use and ability to represent and interact graphically 
with data of the underlying systems, but the add-on nature of the present 
GUIs, especially in the UNIX world, has created certain limitations. With UNIX, 
for example, there are many flavors of the OS and several implementations 
of the basic X-Window technology floating around, so that it’s difficult to 


COMPUTER DESIGN 


Graphical user inter- 
faces now provide 
environments 
where applications 
controlling objects 
can represent those 
objects. GUIs also 
provide client/serv- 
er models and inter- 
process communica- 
tions that let 
networks of nodes 
communicate easily 
with screens to dy- 
namically update 
displays. This plant 
display using 
Wonderware’s In- 
Touch lets you moni- 
tor and interact 
with an animated 
model of the plant. 


DECEMBER 1992 85 


BE TECHNOLOGY FOCUS: GRAPHICAL USER INTERFACES 


realize many of the benefits that a 
truly integrated GUI can bestow, 
such as application portability. In 
the case of MS-Windows, the limita- 
tions are less severe because Micro- 
soft has control of both the Gur and 
the underlying operating system. 


| Integral GUIs add benefits 


A big benefit of an operating system 
with an integral GUI is that it pres- 
ents a solid application program- 


REPLY - - - - 


SEND 


the Os via its API protocols; another 
is to encapsulate a realtime kernel 
such as iRMX, pSOS+ or VRTX on a 
board with a dedicated processor. 
The latter lets the kernels respond 
to interrupts as fast as possible, 
since a user interface isn’t realtime 
anyway, they can still communicate 
with the Gu! on the larger operating 
system via a communication proto- 
col supported by the os’s APt. Or, if a 
large Os represents overkill, there’s 


Windows NT operating system 


POSIX 
SUBSYSTEM 


USER MODE 


KERNEL MODE 


The Windows NT operating system will provide a client/server architecture to make it 
modular over networks. It will also provide compatibility modules, so that applications 
written to programming interfaces other than its own will run in the NT environment. 


ming interface (API) that doesn’t let 
programmers circumnavigate the os 
and directly manipulate the hard- 
ware. An inviolate API ensures porta- 
bility of applications by enforcing 
programming discipline, especially 
if the Os is itself designed to be por- 
table to different processor environ- 
ments (as is the case with Windows 
NT). Such a situation is bound to 
evoke howls of protest from realtime 
developers, however, because they 
insist that they need to get directly 
to the hardware. 

There are two basic ways to meet 
the needs of designers who really 
have to tickle registers or I/O devices 
directly, and yet who want to take 
advantage of the user interface of- 
fered by a large operating system 
such as Windows NT. One way is to 
write hardware drivers that talk to 


86 DECEMBER 1992 COMPUTER DESIGN 


the alternative of inMx for Windows, 
which provides a compact realtime 
kernel as well as access to an indus- 
try-standard GUI. 


BH Anew generation of OSs 


“There’s still a strong contingent 
that believes that UNIX is the wave of 
the future,” says Dennis Morin, pres- 
ident of Wonderware (Irvine, CA). 
“Imagine something that’s been 
around 15 years still being the wave 
of the future.” The candidates for the 
“wave of the future” epithet appear 
to be Windows NT, OS-2 and, perhaps 
surprisingly, NextStep. All have well 
integrated Guls, as well as different 
capabilities when it comes to real- 
time and embedded systems. And all 
have liabilities. OS-2 2.0, for exam- 
ple, is shipping, but sales have yet to 
reach a million copies. Windows NT 


was announced for the first part of 
1993, but is now delayed until sum- 
mer. NextStep was once thought to 
be specialized and restricted to the 
Next machine, but a 486 version will 
put it on mainstream hardware 
where its commitment to object ori- 
entation and visual application de- 
velopment could very well make it a 
strong competitor. 

The most likely winner in this 
race is Windows NT. People seem to 
be waiting for it rather than opting 
for the already available OS-2. One 
thing that will make Windows NT 
suitable, at least for larger realtime 
applications, is that it is pre- 
emptable not only at the task level 
but at the kernel level as well. Even 
if the OS is manipulating some ker- 
nel data structure, then, it can re- 
spond to an external interrupt in a 
deterministic manner. 

Microsoft hasn’t partitioned Win- 
dows NT to have a self-sufficient mi- 
crokernel. “Most folks working in 
process control are doing it with the 
assumption that they’re going to 
take the whole thing and embed it 
in,” says Microsoft’s NT group prod- 
uct manager, David Thacher. 
“There’s a class of applications 
where a full-up version of the os is 
fine, but you wouldn’t use it to con- 
trol a refrigerator.” A full-sized os 
with realtime capability is useful, of 
course, where you need a user inter- 
face, a powerful development envi- 
ronment and a wide choice of devel- 
opment tools. 

Another factor working in favor of 
Windows NT is that its user interface 
is already familiar to millions be- 
cause it’s virtually identical to that 
of Windows 3.1. The actual API is a 
32-bit superset of the present Win- 
dows 3.1 API, which means that well- 
behaved Windows applications will 
run under NT without modifica- 
tion—as 16-bit operations. “Well-be- 
haved” in this context means the 
applications are written faithfully to 
the API and don’t directly manipu- 
late the bus or other hardware. The 
government-mandated security fea- 
tures of NT will forbid such manipu- 
lation in any case. 

Both OS-2 and Windows NT will 
aim to run applications written to 
other APIs. In addition to the Win 32 
interface, for example, NT will in- 
clude modules to let it run programs 
written for Dos, OS-2 and posix, the 
standard interface for UNIX pro- 
gramming demanded by the govern- 
ment to clear up some of the confu- 
sion in the UNIX world. OS-2 includes 


a module to run Windows applica- 
tions, and will also be adding a PosIx 
interface at some point. 

The third potential player in this 
contest is NextStep, which makes no 
pretense of being able to run appli- 
cations written to other APIs, since 
its own user interface is based on 
Display PostScript. Originally con- 
ceived for Next’s proprietary 68030 
machines, NextStep was written in 
Objective C and is being ported to the 
Intel i486 architecture. “Moving to 
the 486 is merely a recompile,” says 
Avidis Tavanian, Next’s director of 
systems software. That goes for the 
applications and object-oriented 
class libraries as well. The object- 
oriented nature of the 
NextStep environment 
and its Interface 
Builder graphical pro- 
gramming tool are ex- 
amples of how GUIs 
are moving the world 
closer to object orienta- 
tion. 

Portability among 
different hardware 
platforms is something 
built into Windows NT 
and NextStep. At the 
moment, however, OS- 
2 is restricted to Intel 
X86 series processors, 
since portions of it 
were written in assem- 
bly language. IBM has 
stated that the next 
version of OS-2, Ver- 
sion 3.0, will be based 
on the Mach kernel, an 
improved version of the 
UNIX kernel developed at Carnegie- 
Mellon University (Pittsburgh, PA). 
The Mach kernel is the same one 
that’s at the base of the NextStep 
operating system; presumably it 
will make OS-2 portable to other 
platforms. 

There’s one caveat about the 
Mach kernel when used in realtime 
systems—while it does allow task 
preemption at the task or thread 
level, the kernel itself isn’t pre- 
emptable. OS-2 is similar in this 
regard in its present version, and 
will presumably be the same in its 
future 3.0 version. This limits its 
applicability for some realtime uses 
that require both very fast response 
and strict deterministic behavior. 
Still, a large number of process con- 
trol and manufacturing applications 
don’t require this extremely tight 
scheduling. “If you understand your 
application and it’s well-behaved,” 


says Tavanian, “[NextStep] provides 
all the capabilities to set up fixed 
priority scheduling on processes or 
threads. Or you can choose to time 
share.” Next itself uses its own ma- 
chines running NextStep to control 
the robots in its automated assem- 
bly operation. 


Bf Windows in embedded systems 


Window environments, both MS- 
Windows and X-Windows, have 
been designed to support cli- 
ent/server architectures. Among the 
most powerful capabilities to come 
along with the Microsoft Windows 
and the OS-2 Guis is the dynamic 
data exchange (DDE) interprocess 


“The industrial automation business,” says Wonderware’s Phil Huber, 
“was once the bastion of proprietary equipment. Everything was propri- 
etary. Now it’s turning into a business built on commodities, and the 
differentiation is software.” 


communication protocol, which 
makes it easy to share data among 
applications. An enhancement to 
DDE, object linking and embedding 
(OLE), lets data created by one appli- 
cation be embedded and even edited 
in another. OLE is aimed mainly at 
creating compound documents and 
appears to the user much as a DDE 
does. Another capability provided by 
both MS-Windows and OS-2 is the 
ability to write dynamic link librar- 
ies (DLLS). DLLs are executable code 
modules that can be loaded on de- 
mand and linked at run time, then 
unloaded when they're no longer 
needed. 

DDE was originally conceived as a 
way for applications running on the 
same machine to share data, but it’s 
also served as an easy means of 
transferring data from a realtime 
node into the Windows-based user 
interface application. Conversely, 


an operator can interact with graph- 
ics objects on a Windows screen—a 
slider control, for example—and 
send values back to a realtime mod- 
ule via a DDE link; these values can 
serve as input commands to the re- 
altime process. Process control de- 
signers have made creative use of 
off-the-shelf Windows applications, 
such as the Excel spreadsheet. Data 
from an embedded node, for exam- 
ple, is sent to a spreadsheet cell, and 
that cell is then linked to an Excel 
bar graph that changes as the cell 
data is updated. 

A natural follow-on step to using 
off-the-shelf business applications is 
to supply graphical tools that let you 
actually model and 
control your system in 
terms of pumps, 
valves, sensors, actua- 
tors, and other physi- 
cal objects in a plant, 
factory or other sys- 
tem. Wonderware sup- 
plies an MS-Windows- 
based package called 
InTouch that lets you 
design screens with 
dynamic graphic ele- 
ments and connect 
them to control sys- 
tems via DDE drivers. 

Windows, of course, 
isn’t itself an object- 
oriented environment, 
but Wonderware sup- 
plies object-oriented 
graphical tools that let 
you build dynamic ob- 
jects. Once the object 
has been drawn, you 
can assign it dynamic charac- 
teristics, including animation. Such 
an object, when saved, can be re- 
called, modified and saved as a sep- 
arate object, or built into some 
larger object. In this way, the user 
interface to a plant can easily be 
modified as the physical plant is re- 
configured. 

Normally, DDE links applications 
running on the same machine, but 
Wonderware has developed a net- 
work version called NetDDE that per- 
mits peer-to-peer communications 
over a network. Each node on the 
network must have a NetDDE driver. 
Wonderware has created drivers 
that support not only different oss 
such as OS-2, UNIX and vs, but also 
a range of programmable logic con- 
trollers commonly used in industrial 
process control, such as those made 
by Allen-Bradley, General Electric, 
Reliance, and others. 


COMPUTER DESIGN DECEMBER 1992 87 


BE TECHNOLOGY FOCUS: GRAPHICAL USER INTERFACES 


And Wonderware has built intel- 
ligence into its DDE drivers. The driv- 
ers have to poll various points in a 
device. Because most drivers send 
data out over a serial line, polling all 
the data points every time one of 
them changed could flood the net- 
work with data in a large system. If 
a system has 50 different screens, 
for example, each screen might call 
up a different subset of the data 
from a given PLC, or might want to 
poll some points more frequently 
than others. “All we want are the 
data points being displayed at the 
time, data points that 
might affect an historical 
database,” says Phil 
Huber, vice-president of 
engineering for Wonder- 
ware. “So every time you 
change a screen, you’ve 
got to redefine the polling 
list.” 

Wonderware has built 
algorithms into the DDE 
servers that can dynami- 
cally allocate the polling 
list to determine how of- 
ten and in what order 
points are polled. The 
server monitors changes 
and only notifies the user 
interface if there is one. 
This report-by-exception 
dynamic polling makes 
feasible systems with 
many nodes and a large 
number of screens. “This 
gives us the ability to de- 
velop an application in 10 to 15 per- 
cent of the time it used to take,” says 
Huber. InTouch doesn’t care 
whether you’re dealing with a DDE 
server to a device that’s local or 
across the net. “The whole purpose 
of NetDDE is to completely hide 
what’s on the other side,” Huber 
adds. 


Bf Building GUIs and applications 


The one thing anyone who’s written 
applications for a windowed envi- 
ronment will agree upon is that a 
GUI involves a lot of complex code. 
Writing C code from scratch to spec- 
ify the pixel dimensions of a window 
or to design a dialog box gets old 
quickly and cuts into a program- 
mer’s productivity. X-Window im- 
plementations such as Motif and 
Open Look have established toolkits 
to help programmers with these re- 
petitive tasks, but these toolkits by 
themselves have turned out to be too 
limited in functionality to let the 
programmer get on with the job. 


88 DECEMBER 1992 COMPUTER DESIGN 


The next stage of development for 
GUIs has been to automate the pro- 
cess of building the user interface to 
an application in terms of the look 
and feel of the operating system GUI. 
This level of programming aid now 
comes in two flavors. The first con- 
sists of interface construction pack- 
ages that run as programs under the 
os. With these programs you can 
create the user interface first and 
then link it to the application code. 
The second type of aid is composed 
of a growing number of program- 
ming language and development 


Devguide from SunSoft runs as a program under Sun's Solaris ver- 
sion of UNIX. It lets you create the menu and dialog items needed 
for a user interface to the application. To do so, it generates an in- 
termediate code that can be used to generate source code, which 
can in turn be linked to the application and compiled. 


products including enhancements to 
help automate building the GUI as 
part of the application code. 

An example of the first flavor of 
aid is Devguide by SunSoft (Moun- 
tain View, CA). Devguide’s latest ver- 
sion runs under Sun’s UNIX- 
flavored Solaris, and uses the 
principles of Sun’s OpenWindows en- 
vironment to permit design and test- 
ing of user interfaces for Open Look 
applications that are compatible in 
look and feel (as well as interopera- 
bility) with the Solaris DeskSet en- 
vironment. The complexity of this 
situation illustrates why a new gen- 
eration of OSs with integrated GUIs 
is emerging. 

To develop a user interface under 
Devguide, you select and combine 
graphic elements such as windows, 
dialog boxes and buttons. You can 
give buttons names and assign help 
text to them. Devguide includes a 
connection manager to let you spec- 
ify source and target objects. A 
source button, for example, can be 


associated with a target pop-up box, 
so that when the button is clicked 
the box appears. Each item also has 
a property sheet associated with it 
to specify name, footer, label, and 
other characteristics. 

One advantage of designing the 
GUI in an interactive manner, such 
as that provided by Devguide, is that 
you're setting up the specification of 
the program either by following some 
prewritten specification or by intui- 
tively defining how you want the ap- 
plication to work before you write any 
code. Devguide produces an interme- 
diate code that can be used 
with code generators to 
produce C, C++ or Ada 
source code. Interface ob- 
jects produce code stubs 
that connect to corre- 
sponding functions in the 
application. The GUI 
source can then be linked 
and compiled with the 
application code. 


HB Bundled GUI tools 


In operating system en- 
vironments that have a 
single, standard Gui— 
Windows, Windows NT, 
OS-2 and NextStep, for 
example—vendors of pro- 
gramming languages 
can afford to include GuI 
development tools with 
their products. The 
Turbo C++ compiler and 
programming environ- 
ment from Borland International 
(Scotts Valley, cA), for example, in- 
cludes tools to create Windows user 
interfaces for applications on three 
levels. One can, of course, always 
write C code to call the Windows API 
directly, but Borland includes a facil- 
ity called ObjectWindows that uses 
a library of C++ objects to encapsu- 
late Gul functions. So, instead of 
writing 50 lines of C code to set up 
data structures, register the appli- 
cation with windows and perform 
other functions, you write a few 
lines of C++ with some parameters 
that call the ObjectWindows library. 

The third method is to create win- 
dows, boxes, menus, and other ob- 
jects interactively on the screen us- 
ing a tool called Resource Workshop. 
The objects then generate C++ code 
as part of the application. 

“What Windows needs to be ob- 
ject-oriented,” says Borland’s C++ 
product manager, Charles Dicker- 
son, “is to encapsulate the API so that 
you have functional objects to plug 


A dynamic object created with the Dynamics/V Object Construction Kit can have a 
number of roles assigned to it by embedding other objects. Then, depending on the 
type of message sent to it, it will respond in the proper role. Objects embedded in a 
dynamic object can be changed, added to or replaced as the situation demands—and 
without disturbing the other areas of functionality of the dynamic object. 


into the application instead of doing 
all this C interaction.” Turbo C++ 
ObjectWindows does this with a 
mechanism called dynamically dis- 
patched virtual tables (DpvTs), which 
replace the nested switch statements 
required by the API for objects that 
can inherit response functions, such 
as “Open a box.” ObjectWindows, 
then, lets the application and its 
user interface be object-oriented, 
even if the os and its GUI aren't. 


| NextStep the next step? 


Taking a step closer to a GuI-based, 
object-oriented environment that in- 
cludes object-oriented program de- 
velopment is the NextStep Interface 
Builder. With it, objects supplied by 
Next or third-party software devel- 
opers are represented as graphic 
icons and can be interactively con- 
nected on the screen. Interface 
Builder is run-time bound, so that 
as soon as two objects—a slider bar 
and something it controls, for exam- 
ple—are connected together and 
their relative scales defined, the 
slider can directly control the object. 
In this way you can test the func- 
tioning of the program as it’s 
developed. 

With NextStep, objects are cre- 
ated in Objective C and can be rep- 
resented as icons, as can user inter- 
face objects. The difference is that 


the former won’t appear on the 
screen when the application is run. 
This has given rise to a group of 
software vendors whose products 
are class libraries rather than pack- 
aged applications. You can put to- 
gether the major parts of a generic 
application by simply hooking to- 
gether these objects. Then you can 
add value or address your special 
needs by either modifying one or 
more of the objects in the library or 
writing new objects of your own. 


Ha two-way street 


Object-oriented languages are tak- 
ing cues from GUIs as well as the 
other way around. Smalltalk, for ex- 
ample, is a language that was de- 
signed from the ground up to be 
object-oriented. Objects are re- 
trieved from class libraries as pieces 
of source code and built into applica- 
tions. Recent versions of Smalltalk 
for Windows and OS-2, developed by 
Digitalk (San Diego, CA), have in- 
cluded objects that let you graphi- 
cally construct windows, dialog 
boxes and other user interface ele- 
ments for the application under de- 
velopment. The GuI elements exist 
in a class library, just as other 
Smalltalk objects do. Recently, Dig- 
italk introduced a product called 
PARTS (for Parts Assembly and Reuse 
Tool Set) that lets Smalltalk objects 


be represented graphically and as- 
sembled using an environment 
called the PARTS Workbench. Cur- 
rently available under OS-2, PARTS 
will also be ported to Windows and 
Windows NT. 

A third-party vendor, s1 Data- 
service (Munich, Germany), has de- 
veloped a similar graphical develop- 
ment environment. Called Dynam- 
ics/V, it runs on top of Smalltalk/V 
and other flavors of Smalltalk. Dy- 
namics/V uses an object construction 
kit to browse class libraries, connect 
graphical icons that represent clas- 
ses, form objects, and ultimately cre- 
ate applications. The construction 
kit lets you create a dynamic object, 
or a “software Ic,” with as many 
“roles,” or modes of behavior, as can 
be assigned to that class. 

The implication of this capability 
for general-purpose interrupt drive 
systems is that response can be built 
easily into automation systems, be- 
cause the interfaces between objects 
are already defined. As the require- 
ments of the application change, 
roles can be added or subtracted—in 
terms of existing objects, objects con- 
structed or modified with multiple 
objects, or custom-created objects 
that then add to the existing reper- 
tory. In this context, there could be 
interrupt service objects that let an 
application be set up with as many 
roles as needed and without having 
to be altered in other ways. ba 


For more information about the technol- 
ogies, products or companies mentioned 
in this article, call or circle the appro- 
priate number. 


Borland International 


(800) 331-0877 .. Circle 249 
Digitalk 

(213) 645-1082 .. Circle 250 
Intel 

(800) 547-8806 .. . yislaularens Circle 251 
Microsoft 

(800) 426-9400 Circle 252 
NeXT Computer 

(800) 848-6398 Circle 253 
SI dataservice 

(619) 322-2761 . Circle 254 
Sun Soft 

(415) 336-0678 Circle 255 
Wonderware 

(714) 727-3200 Circle 256 


COMPUTER DESIGN DECEMBER 1992 89 


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32-bit power and tools 
bring cheer to embedded 
system designers 


Because of their increased compute power, higher integration, 
extensive tool sets, and a desire for the friendliness provided 
by high-level languages, more designers are putting 32-bit 
microcontrollers on their wish lists for next-generation products. 


| een? processors and microcontrollers have moved beyond 
PostScript printers into industrial controllers, multimedia devices and 
telecommunications bridges and routers. A number of new micro- 
controllers, support ASICs and boards are making it easier than 
ever to bring a 32-bit product to market at an economical price. 
At the same time, an equally impressive array of new prod- 
ucts from software development companies and emulator 
suppliers is simplifying development, hard- 
ware integration and debugging. 

This doesn’t signal the end of the 8051- 
based household appliance controller, 
it’s just that these newer applications 
require the processing and data- han- 
dling speed, as well as the 
address space, of 32-bit 
» engines. In some cases, too, 
“Ait isn’t raw power that 
drives development 


Se" 7—= Don Tuite, Senior Editor 


BSPECIAL REPORT: 


teams to 32 bits, but the 
need for the program- 
mer-friendliness and 
documentability that 
high-level languages pro- 
vide. The price paid for 
high-level programming, 
however, is larger object 
modules. 

Some observers find 
that the shift from a hard- 
ware-driven approach to 
embedded systems design 
to a software-driven ap- 
proach signals a water- 
shed opportunity for both 
tool and chip makers. “I’ve 
seen a lot of 32-bit appli- 
cations that would run 
just fine on 16- or even 
8-bit processors if the 
code were written in as- 
sembler,” says Charles 
Davis, president of 
Huntsville Microsystems 
(Huntsville, AL), half-jokingly. Davis 
also notes another shift in the devel- 
opment scenario. At the same time 
that company or contract require- 
ments impose C++ or Ada program- 
ming restrictions, the complex nature 
of the embedded task creates a need 
for developers who are more familiar 
with the end application than with 
silicon architectures. Vendors of chips 
and development tools have noted 
this trend and are standing by with 
“solutions,” as the marketers say. 


B Not just RISC 


The technical press’s fascination with 
RISC sometimes obscures the 32-bit 
design wins that Motorola’s 68000 
and its 68000-based 683XX microcon- 
troller family have piled up. Mo- 
torola’s (Austin, TX) continuing suc- 
cess is at least partly due to the length 
of time the 68000 and its offspring 
have been around. As Kenneth 
Greenberg, director of technical mar- 
keting at Microtec Research (Santa 
Clara, CA) says, “The overwhelming 
majority of embedded system design- 
ers said they used the same processor 
used in their last project, or at least a 
member of the same processor fam- 
ily.” And as Ed Rathje, vice-president 
of sm Software Consultants (Spring- 
house, PA) notes, “Most of the engi- 
neers now doing embedded designs 
graduated from college knowing 
68000 assembler.” 

The two most general-purpose 
members of the 68300 family are the 
68331 and 68332. The 68331 strips 
out the 68332’s sophisticated time- 
processing unit and its 2 kbits of SRAM. 


92 DECEMBER 1992 COMPUTER DESIGN 


32-BIT MICROCONTROLLERS 


Using his company’s present-generation emulator to design the 
next generation, Embedded Performance’s Ted Conard tracks over- 
shoot on a clock signal. A senior hardware development engineer, 
Conard agrees that the type of person designing embedded sys- 
tems is changing. “We see a different kind of customer using 
[AmpD’‘s] 29200 than we did using the older chips,” he says. 


Both are aimed at applications such 
as automotive controllers. 

In contrast, the 68340 has a differ- 
ent timer module than the 330 parts, 
plus a dual-channel DMA controller ca- 
pable of 33-Mbyte/s speeds. It targets 
multimedia applications. There are 
now 5-V and 3.3-V versions of the 
68340. At the top of the 68300 perfor- 
mance scale, the 68302 has a DMA 
controller and a separate three-chan- 
nel communications processor. It’s 
aimed at telecommunications. 

Motorola offers embedded control 
versions of its 68000/020/030/040 mi- 
croprocessors as well. In this case, 
embedded control means that the part 


is stripped of MMU, which 
results in a price about 
half that of a full-fea- 
tured chip. 

Adding field-pro- 
grammable elements to 
32-bit microcontrollers 
was pioneered by Mo- 
torola in 1991. There are 
currently two objects of 
programmability: to pro- 
vide for design changes 
late in the cycle, or to 
supply security features, 
such as the ability to pro- 
gram serial numbers at 
the time the chip is as- 
sembled onto a board or 
to install data encrypt- 
ion keys. 

With programmabil- 
ity in mind, Motorola’s 
68300 microcontroller 
family includes the 
68F333, with a flash EE- 
PROM on-chip. The 68F333 continues 
to be the only 32-bit microcontroller 
with on-board reprogrammable 
memory. This October, however, VLSI 
Technology (San Jose, CA) introduced 
programmable functional system 
blocks (pFSBs), ASIC PROM and PLD 
elements that can be embedded 
along with ARM (Advanced RIsc Mi- 
croprocessor) 32-bit processor cores. 
These are one-time programmable 
elements, based on the ViaLink an- 
tifuse technology jointly developed 
by visi Technology and QuickLogic 
(Santa Clara, CA). The 68F333 incor- 
porates 64 kbytes of flash. The larg- 
est of vLsI Technology’s pFSB ROMs is 


CASP RISC design 


CUSTOMER 


PROPRIETARY CUSTOMER 


SEA OF GATES 


(CUSTOMER TREATS THIS 
BLOCK AS AN ASIC) 


SYSTEM I/O 


SCSI 


ETHERNET 


SUBSYSTEM BLOCKS 


DATA IN 


DATAPATH 
CONTROL VO 


<a) 


UART 


DATA OUT 


Not all 32-bit embedded design is for the hardware-challenged. The alternative to 
letting your silicon vendor do all the fun stuff is epitomized by S-MOS’s CASP. If you 
have an unusual application that requires finesse, you can fine-tune the RISC architec- 
ture of the CASP ASIC's datapath. You can, for example, select exactly which instruc- 
tions will make up your instruction set, and you can even provide for the launch of 


up to four instructions per clock cycle. 


Selecting a 32-bit microprocessor for embedded applications 


S. you've de- 


cided that your 
next project will be 
based on a 32-bit 
microprocessor, but 
which one will you 
use? There are a 
number of factors 
——— to evaluate, and 
the most significant may be the proces- 
sor used in your last application. The 
overwhelming majority of embedded 
system designers I've interviewed re- 
cently said they reused the same proces- 
sor used in their last project, or at least 
a member of the same processor family. 
But what if you’re currently using an 
8- or 16-bit processor and you have the 
freedom to select any architecture that 
meets the needs of your application? 
You'll have to analyze those needs care- 
fully, and ask yourself some questions. 


E Price, performance important 


Historically, price and performance have 
been primary criteria in processor selec- 
tion. While price may still be an over- 
whelming reason to select a processor, 
performance may not. If you’re moving 
up from an 8- or 16-bit application, 
you're likely to find that any of the 32- 
bit processors available will give you 
more than enough power to meet the 
needs of your design. Despite the ongo- 
ing arguments about cisc vs risc, either 
approach is likely to satisfy the perfor- 
mance needs of most applications. riscs 
tend to run somewhat faster, since their 
large register sets minimize memory ac- 
cesses. Their simple instruction sets, 
though, mean they require more instruc- 
tions to do the same work as CISC proc- 
essors. Plan on having more memory 
available for storing your code if you 
base your design on a Risc chip. 

A more interesting point to consider 
may be the level of integration available 
to you. The simplest microprocessors 
consist of only the cpu itself. Many mi- 
croprocessor families include some 
members called high-integration parts, 
which add various kinds of peripherals 
to the basic cpu design. Some peripher- 
als are general-purpose, while others 
may be tailored to a specific kind of ap- 
plication. Higher integration means a 
lower chip count and less real estate 
needed on your board. For embedded 
applications, where physical size is often 


an important limitation, this may be criti- 
cal. It also may help reduce the cost of 
your product. At the very least, fewer 
parts will simplify your design. 

At the most basic level, higher integra- 
tion may simply be the presence of an 
on-chip floating-point coprocessor. If 
your application makes extensive use of 
floating-point computation, your prod- 
uct may not be competitive without a co- 
processor. But the FPu is just the most ob- 
vious in a long list of available devices. 
Do you need counter-timer circuits? 

Most embedded applications do, at least 
for realtime clock generation or watch- 
dog timers. Some microprocessors will 
have these available on-chip, saving you 
the trouble of adding them externally. 


B Watching for gremlins 

How critical is the ability to catch mem- 
ory access violations before they destroy 
valuable data—or perhaps the system it- 
self? For some mission-critical applica- 
tions, you may wish to consider proces- 
sors that have an on-chip mMMu. You may 
not need it for managing virtual mem- 
ory, but the mmu can provide basic pro- 
tection services that detect attempts to 
write into memory that you really in- 
tended to be read-only. In a small sys- 
tem, you might wish to select a proces- 
sor with the capability of providing 
chip-select signals for memory or periph- 
eral devices. You may be able to elimi- 
nate address decoding logic on your 
board if the microprocessor can do it. 

While applications that run on 32-bit 
processors are almost always written in 
high-level languages such as C, most 
embedded applications contain at least 
some assembly language. While any mi- 
croprocessor can be programmed in as- 
sembly language, some are easier to 
deal with than others. If your software 
engineers know Intel 8086 assembly lan- 
guage really well, then assembly lan- 
guage for the 386 or 486 is a relatively 
small step to take. Motorola 68000 as- 
sembler is widely known and easy to 
learn, and is similar to the assembly lan- 
guage used by several 8-bit cpus. 

In contrast, the three-operand style of 
assembly language used by most risc 
processors takes some getting used to. 
For most Riscs, specifying a memory ad- 
dress and fetching its contents takes 
three separate instructions. You should 
plan to study the assembly language 


produced by your compiler to learn how 
to perform such basic operations. 

Another basis for selecting a proces- 
sor is the availability of support tools. 
Do you need in-circuit emulation? Many 
vendors provide emulators for cisc chips 
such as the Motorola 68000 family. You 
can select the one that best meets your 
needs. For a RISC processor, your choices 
will be more limited—or, there may not 
be an emulator available at all. There 
are certainly alternatives for debugging 
if no emulator is available, such as in-cir- 
cuit monitors. These can even be left in 
your product for debugging in the field. 
However, emulators are particularly 
good at solving hardware/software inte- 
gration problems. It’s generally useful to 
have one around for debugging prob- 
lems when your hardware isn’t fully 
working yet. 


& Using what's available 

Are you familiar with one of the com- 
mercially available realtime kernels? If 
so, you may wish to consider a proces- 
sor for which that kernel is available. 
This will save you the trouble of learn- 
ing a new operating system. Even if 
your application isn’t going to use a real- 
time kernel, your next project might. Re- 
member, you're likely to use the same 
processor you choose today in tomor- 
row’s project, unless you want to start 
over with selecting hardware and soft- 
ware development tools. 

You may wish to take advantage of the 
power and larger address space provided 
by 32-bit processors and implement your 
application in an object-oriented lan- 
guage such as C++. You can expect to 
get future products to market more 
quickly if you take advantage of the re- 
usable code provided by C++, but it isn’t 
available for all 32-bit processors yet. 

Finally, you may wish to consider that 
software development is moving from 
the Pc environment to UNIx workstations 
in many companies. This has improved 
productivity, but has caused some prob- 
lems with compatibility. Almost any Pc 


can run a PC application, but all UNIX 
workstations are different. Make sure 
the tools you need are available in the 
development environment you have 
chosen. 


Kenneth F. Greenberg, BA in computer science, Microtec Research, Santa Clara, CA 


COMPUTER DESIGN DECEMBER 1992 93 


ESPECIAL REPORT: 32-BIT MICROCONTROLLERS 


CONTROLLER 


PARALLEL PORT 
CONTROLLER 


2 CHANNEL BUS INTERFACE cLock 


CONTROLLER DRIVERS 


DMA 
CONTROLLER 


TIMER AND STATUS 
REGISTERS 


HIGH SPEED 
SERIALIZER/ 
DESERIALIZER 


DATA BUS 
CONTROLLER 


EXTERNAL 
MEMORY. 
CONTROLLER 


REGISTER FILE 
EXECUTION UNIT 


AMD’‘s AM29205 RISC microcontroller is typical of the latest generation of highly inte- 
grated chips. The 205 is also an unabashed effort to capture design wins from 16-bit 
competitors. While it retains the 32-bit 29000 core, making it compatible with other 
members of the family, the datapath width has been trimmed to 16 bits. Despite hav- 
ing to use two clock cycles to load an instruction, the 205 offers better price-perfor- 
mance than 16-bit CISC competitors, according to AMD. 


512 x 32 bits. Details on the com- 
pany’s PLD elements haven’t yet 
been announced. 


B Anew generation for the 29000 


Another mature 32-bit product with 
a large number of design wins and 
an assortment of new microcon- 
troller chips is the 29000 from Ad- 
vanced Micro Devices (AMD—Austin, 
Tx). The company’s first 29000-ar- 
chitecture microcontroller was the 
16-MHz 29200, with a full 32-bit 
core plus timer and memory and 
interrupt controllers, but no on-chip 
cache. In September, AMD intro- 
duced an economy version of the 
29200, the 8-Mips 29205, which cou- 
ples the family’s 32-bit core with a 
16-bit bus and an inexpensive 100- 
pin PQFP package. Intended to lure 
designers away from 16-bit CISC 
chips such as the 80186, the 29205 
has greater performance than the 
186 at a competitive price. 

Even at its introduction in 1988, 


94 DECEMBER 1992 COMPUTER DESIGN 


Intel’s (Chandler, Az) i960 offered an 
integrated half-kilobyte instruction 
cache along with the processor core. 
At that time, the civilian members 
of the family consisted of the i960KA 
and kB. The kB has a floating-point 
unit; the KA doesn’t. 

The lower-cost members of the 
family, the i960SA and sp, trim the 
external data bus to 16 bits, but 
retain the instruction cache. There’s 
also an integrated interrupt control- 
ler that can handle up to four direct 
interrupts. The SB has an FPU. 

The newest members of the fam- 
ily, the 1960CA and CF, are supersca- 
lar, launching two instructions per 
clock cycle, at 16 and 33 MHz re- 
spectively. Relative to the earlier 
chips, the i960cA upgrades the cache 
from direct-mapped to two-way set- 
associative and increases its size to 
1 kbyte. The i960cF has a 4-kbyte, 
two-way set-associative instruction 
cache and a 1-kbyte, direct-mapped 
data cache. Both of the superscalar 


chips integrate 1 kbyte of data RAM, 
four DMA channels and an interrupt 
controller that can handle up to 248 
external interrupts. 


Bf R3000-based controllers 


AMD’s 29000 seized an early advan- 
tage in the cost-sensitive embedded 
arena thanks to its ability to inter- 
face directly to DRAM. This advan- 
tage is now eroding as members of 
other silicon vendors’ families, such 
as the R3041 from Integrated Dev- 
ice Technology (Ipt—Santa Clara, 
CA), offer similar capabilities. 

IDT’s MIPS R3000 controller family 
comprises the high-end R3081, with 
FPU and instruction and data cache 
(16 and 4 kbytes, respectively); the 
midrange R3051 and R3052, with- 
out the FPU and with smaller caches 
(4 or 8 kbytes of instruction cache, 2 
kbytes of data cache); and, just in- 
troduced, the low-end R3041, with 2 
kbytes of instruction cache, half a 
kbyte of data cache and some inter- 
esting special features. 

The special features include pro- 
grammable bus widths. The idea is 
to simplify the task of accessing 16- 
bit printer font caches and 8-bit boot 
ROMs, without sacrificing the advan- 
tages of a 32-bit bus for addressing 
memory and loading instructions in 
a single cycle. Four-level read and 
write buffers speed up memory 
operations. 

The chip holds addresses longer— 
half a cycle past address latch en- 
able—than conventional RISC chips, 
simplifying the interface to ASICs 
and FpGAs. The R3041 also provides 
fixed-map address translation in- 
stead of a translation look-aside 
buffer (TLB). The silicon real estate 
that was recovered from the TLB is 
used for an event timer. 

IpTt’s 3081 illustrates one of the 
dilemmas inherent in creating chip 
families. As the highest-power, most 
fully featured member of the family, 
it seems logical that it be the one to 
incorporate the FPU. The reality of 
the market, however, is that the 
high end is dominated by telecom- 
munications applications such as 
routers and bridges, which don’t re- 
quire floating-point computations. 

“We’re finding that telecom- 
munications customers are ignoring 
the FPU and concentrating on the raw 
power of the chip,” says IDT’s director 
of RISc marketing, Bob Rowe. 

For the SPARC RISC camp, the mi- 
crocontroller candidate of choice is 


continued on page 99 


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BSPECIAL REPORT: 32-BIT MICROCONTROLLERS 


continued from page 94 


Fujitsu’s (San Jose, CA) SPARClite. 
Two years ago, Cypress Semicon- 
ductor (San Jose, CA) introduced its 
CY7C611 SPARC processor for em- 
bedded applications. According to 
Joe Nichols, marketing director for 
Cypress’ Ross Technology subsid- 
iary, this part “has a number of re- 
spectable design wins.” Cypress, 
however, hasn’t yet entered the mi- 
crocontroller arena. 

At $179 in 10,000-unit quantities, 
microSPARC from Texas Instruments 


(Dallas, Tx) targets low-end work- 
stations. The chip, however, has in- 
teger and Fpus, 4 kbytes of instruc- 
tion cache and 2 kbytes of data 
cache, MMU and DRAM, SBus, and 1/O 
controllers on-chip, so it isn’t hard to 
envision microSPARC winding up in 
high-end embedded applications. 
Below the $100 price barrier, Fu- 
jitsu’s spARClite microcontroller fam- 
ily offers the greatest number of 
choices. SPARClite represents the 
other horn of the controller family 
dilemma. In its processor core, it 
provides an integer unit only—no 


A(31:0) 


ADDRESS REGISTER 
ADDRESS 
at INCREMENTER 
(31 32-BIT REGISTERS) 


REGISTER BANK 
(6 STATUS REGISTERS) 


ALE 


PC BUS 


ALU BUS 


ARM6 block diagram 


BOOTH'S 
MULTIPLIER 
BARREL 
SHIFTER 


MCLK 
WAIT 


B/w 
RW 


INCREMENTER BUS 


IRQ 
FIQ 


RESET 


INSTRUCTION ABORT 


DECODER — 
& OPC 


TRANS 
M(4:0) 


CONTROL 
LOGIC 


PROG32 
DATA32 
BIGEND 
LATEABT 


B BUS 


MREQ 
SEQ 
LOCK 


CPI 
CPA 


CPB 


DBE —>| WRITE DATA REGISTER 


INSTRUCTION PIPELINE 
& READ DATA REGISTER 


— 


= 


DIN (31:0) 


The architecture of the advanced RISC microprocessor (ARM), manufactured by VLSI 
Technology, is less familiar than other 32-bit options. Shown is the ARM6 CPU core 


that can be integrated as an ASIC cell. It has a full 32-bit address bus, rather than the 
26-bit bus of its predecessor, with which it maintains backwards compatibility. ARM's 
strengths are small die size, low power consumption and the ability to handle either 
big-endian or little-endian data. The instruction set is large for a RISC processor; to 
handle it, VLSI Technology offers a C compiler, symbolic debugger and an emulator. 
Of the 31 general-purpose registers in the block diagram, 16 (including the program 
counter) are available in user mode. The remainder are mapped across ARM's inter- 
rupt, fast interrupt and supervisor operational modes. 


floating point, even though Post- 
Script manipulations involve a great 
deal of floating-point manipulation. 
Fujitsu product marketing engineer 
Peter von Clemm says that Post- 
Script printers will pay a modest 
performance penalty for handling 
floating point in software, but that 
this is outweighed by the price ad- 
vantages of the family. 

Three new members of Fujitsu’s 
SPARClite family have joined the 
MB86930 processor, which debuted 
in 1990. The 20-/40-MHz 931 retains 
the first-generation chip’s 2-kbyte 
instruction and data caches, bus in- 
terface with DRAM control, and inter- 
face to an emulator bus, while add- 
ing four counter/timers, interrupt 
controllers, and two serial channels. 
(The 930 used a companion chip, the 
MB86940, for these functions.) Gone 
is the 930’s translation look-aside 
buffer. 

In contrast, the 932 is more like a 
930 with bigger instruction and data 
caches (of 8 and 2 kbytes, respec- 
tively). It retains the TLB of the 930 
but does without the timers, inter- 
rupt control and usartTs of the 931. 

Priced under $25 in quantity, the 
20-MHz MB86933 is the price leader 
of the sPpARClite family. To achieve its 
low price, it strips out cache, coun- 
ter, timers, USARTs, and interrupt 
control. Also gone is the emulator 
interface, under the assumption 
that you would develop your appli- 
cation using a 930 or 931. 


B Third-party choices 


The level of integration that micro- 
controllers add to bare processors is 
just one advantage these new parts 
introduce. Third-party vendors can 
further reduce time-to-market by 
providing application-specific hard- 
ware and software using various sil- 
icon vendors’ microcontrollers, but 
at a price. The ImageCard 8500 fam- 
ily from Adaptec (Milpitas, ca), for 
example, combines the company’s 
printer ASICs with various AMD 
29000-family processors and micro- 
controllers. vist Technology’s LPIC is 
a controller chip you can use on your 
own board. 

Alternatively, you can use DP- 
Tek’s (Wichita, KS) TrueRes asics to 
create printers with software-select- 
able multiple levels of resolution. 
Phoenix Technologies (Norwood, MA) 
offers software PostScript and PCL- 
5 emulators that are 100-percent 
compatible with the Apple Laser- 
Writer Ig, the Tektronix Phaser II 
PXi and the up LaserJet III. Power- 


COMPUTER DESIGN DECEMBER 1992 99 


BSPECIAL REPORT: 32-BIT MICROCONTROLLERS 


Page, from Pipeline Associates 
(Morris Plains, NJ), also supports 
PostScript. 

If youre not developing a printer, 
TeleSoft International’s (Collier- 
ville, TN) FRAME Relay software 
works with the same processors to 
create WAN products. XLNT Designs 
(San Diego, CA) offers to do the same 
for FDDI networks. 

There are also third parties lined 
up to give you a hand with manufac- 
turing. Circuit Components (Tempe, 
Az), for example, has under-chip de- 
coupling capacitors personalized for 
popular processor and microcon- 
troller packages. For prototyping, 
McKenzie Technology (Fremont, CA) 
provides an adapter that changes 
the 29205’s parP pin-out arrange- 
ment to a pin grid array. 


Bl Getting your hands dirty 


Many silicon manufacturers are go- 
ing out of their way to insulate cus- 
tomers who are from the software 
side from exposure to the raw archi- 
tectures of their products, but ASIC 
vendors with 32-bit cores are taking 
the opposite approach. 

The 16-MHz, 7-Mips ARM is a 
product for mass-market applica- 
tions created by Acorn Computers 
(Cambridge, England), Apple Com- 
puter (Cupertino, cA) and vist Tech- 
nology. To appeal to both hardware 
and software types, VLSI Technology 
lets you either create your own cus- 
tom Asics with ARM processor cores 
or use ARM microcontroller products. 
There are a number of ARM ASIC 
cores, for example, but the ARM250 
microcontroller, announced in Sep- 
tember, contains a 32-bit RISC proc- 
essor, memory, video and 1/0 control- 
lers, and a pc bus interface. It 
interfaces directly to DRAM and ROM. 
Video and sound (svGA and stereo) 
capabilities include on-chip digital- 
to-analog converters. 

The asic vendor who goes farthest 
in encouraging customers to play 
with chip architecture is S-Mos (San 
Jose, CA). You can actually fine-tune 
the RISC processor core in the com- 
pany’s CAsP (Configurable Applica- 
tion-Specific Product) Asics. In fact, 
you can even go so far as to add 
instructions to the RISC instruction 
set if it helps your application run 
better, according to SMOS manager 
of strategic marketing, Dr. Richard 
Ahrons. 

You don’t need an in-depth knowl- 
edge of silicon processing to use 
CASP, either. Even for the small de- 
velopment team, in fact, Ahrons 


100 DECEMBER 1992 COMPUTER DESIGN 


says there’s no need to be daunted 
by the prospect of creating a “tuned 
architecture” processor core or other 
high-level functional block. s-Mos is 
a Seiko Epson affiliate, and the com- 
pany is prepared to make its consid- 
erable design resources available to 
customers. 

To keep development time under 
control, manufacturing CASP prod- 
ucts follows the semicustom ASIC 
model. s-Mos starts fabbing wafers 
as soon as you have defined the ar- 
chitecture, but the company holds 
them short of metallization until 
you've designed the control logic. 


| Developing a product 


In some ways, developing a 32-bit 
embedded product is just like devel- 


oping any other embedded product. 
At least the steps are the same. 
However, says Applied Microsys- 
tems’ (Redmond, WA) vice-president 
of new business development, Dick 
Jensen, “Managing the development 
effort is tougher. The team is bigger, 
the code’s bigger, and you need more 
discipline.” 

Jensen agrees that programmers 
for 32-bit systems are different from 
their assembly-writing counter- 
parts, who work with narrower 
buses and longer instruction sets. 
He says, “The complex nature of the 
applications means that we’re forced 
to get programmers from other 
places. So they know little about 
embedded systems. Our job is to 
change the hostile physical world of 


XTAL1/ 


Fujitsu’s SPARClite 


CLKIN 
con | OR 
CLOCK 
GENERATOR 
& PLL 
CLK SPARC 
OUT INTEGER UNIT 


BUS 
INTERFACE 
UNIT 


DEBUG 


INSTRUCTION 


SUPPORT 
WITH OUTPUT 


DRAM 
SUPPORT 


TO 
EMULATOR 


INSTRUCTION 


BUS 


(ALL EXCEPT 
933) 


16-BIT 
TIMER 


DATA DATA 


DATA ADDRESS 


ADDRESS 
DECODE 


| CACHE 


[__]ALL DEvicEs 


USARTS. 


D CACHE 


INTERRUPT 
CONTROL 


[__]930, 931, 932 4 COUNTER! 
TIMERS 

[]931 ONLY 

[_]932 ONLY 


Using chips with a high degree of integration makes designing your application eas- 
ier—once you've decided what you want integrated. For instance, every member of 
Fujitsu’s SPARClite family integrates the integer unit and bus control. Most integrate 
the emulator bus interface. After that, you get to choose: cache (the 930 has 2 
kbytes, the 932, 8 ytes) or no on-chip cache, data cache size (2 kbytes for both the 


930 and 932) if y« 
and TLB are furthe options. 


choose on-chip cache. Serial interface, timer, interrupt control, 


Choosing development tools: a microprocessor vendor's viewpoint 


i aa of 


embedded systems 
who use Motorola's 
68000 and 68300 
families have relied 
on a wide range of 
development soft- 
ware and hard- 
ware. Helping them 
bring their products to market has 
shaped my own ideas about tools and 
the reasons that people choose them. 

Often, companies pick tools simply 
because they fit into their existing in- 
stalled base of development tools. Un- 
less they are really dissatisfied with what 
they've been using, they find it desir- 
able to upgrade what they already 
have. That only makes sense. The cost 
of starting from scratch is high, and a 
learning curve that takes months puts a 
company at a disadvantage in getting a 
new product to market. 

Even if the tools represent a new gen- 
eration, the deciding factor can be as 
simple as whether a particular tool runs 
on the platforms the development team 
already has (or has decided it can afford). 


y Checking out competing RTOSs 
Embedded systems that require a pre- 
dictable response time to system events 
or that involve a risk of data loss, dam- 
age to equipment or injury to personnel 
obviously must run under a realtime op- 
erating system. A sensible starting point 
for evaluating an RTOS is to ask how well 
it’s regarded in the embedded systems 
community. How long has it been 
around? What is the general opinion re- 
garding the quality of the kernel code? 

Something worth considering at the 
same time is the reputation of the com- 
pany offering the tool with respect to 
technical support. Applications develop- 
ment isn't a suit-and-tie, 8-to-5 busi- 
ness, and engineers and programmers 
often do their most productive work at 
odd hours of the night. That’s why a 24- 
hour hotline can be important. 

In matching an RTOs to the applica- 
tion, the trick is not to reinvent the 
wheel by writing your own code for 
things such as task swapping and vo. If 
the company supplying the kernel can 
also supply the right vo drivers for a par- 
ticular application, that substantially re- 
duces time-to-market for the applica- 
tion developer. Similarly, if the 


application requires higher-level ser- 
vices, such as a file system or a network- 
ing layer, it can save even more time if 
those are available with the rtos. Also, a 
high-level debugger for the RTOs kernel 
is just as important as a symbolic debug- 
ger is for the compiler. The issue again 

is cutting the fat out of the develop- 
ment cycle. 

Obviously, an important key to an 
RTOS is predictable response time. Ven- 
dors of rToss provide tables or formulas 
you can use to determine response time 
for specific tasks, based on what other 
tasks are currently running. In some 
cases, the formulas may include varia- 
bles; this means that, for certain kernel 
services, response times wouldn't really 
be deterministic. This may or may not 
be critical. 

On a more mundane note, the os li- 
censing structure can also influence the 
purchasing decision. Is there a fixed 
price for a single copy, with a sliding 
scale for multiple copies? Are site li- 
censes available? 

At a level above the os, the choice of 
a compiler depends mainly on contract 
requirements or on the philosophy of 
the group developing the application. 
Ada may be a requirement on a govern- 
ment contract. C++ may suit a company 
committed to reusable code and the ad- 
vantages of object-oriented program- 
ming. On the other hand, because of 
the large number of programmers who 
are familiar with it, C continues to be 
the language of choice for most new 
systems. Regardless of the HLL (high- 
level language) symbolic debug is neces- 
sary—that is, debug tools that under- 
stand the compiler is essential 


Bf The emulation trap 

To rely or not to rely on in-circuit emula- 
tion boils down to a philosophical issue. 
These days, we're seeing a trend in which 
our most sophisticated customers use far 
more up-front simulation, and depend far 
less on target debugging using emulators. 
It's a sign that more attention should be 
paid earlier in the cycle as to how the de- 
sign is going to work. 

From a time and a dollar standpoint, 
getting it right in simulation before you 
commit to hardware is easier if there are 
ASICS as Well as a microprocessor on the 
board. It may be every bit as expensive 
in terms of dollars and time to revise a 


board as it is to revise silicon, but not be- 
ing able to back-wire around a problem 
on an Asic the way you can on a board 
makes the situation more absolute. 

Simulation notwithstanding, develop- 
ers can’t completely walk away from 
emulation, and this presents something 
of a challenge to microprocessor manu- 
facturers. A highly integrated microcom- 
puter, or even just a powerful processor 
with on-chip cache, can operate for 
some time by accessing internal re- 
sources, without giving any indication 
to the outside world as to what's hap- 
pening internally. 

To deal with this, we provide hooks 
for debugging. For example, we have a 
mode in which we essentially put the 
processor to sleep and let the emulator 
mirror the processor externally. Our 
newer 68300 family of processors has a 
special debug-mode port, an alternative 
to using an emulator probe when the 
device is in a surface-mount package. 
Depending on the processor you select, 
the lack of silicon-vendor-supplied fea- 
tures like these may limit your choice of 
emulators. In-circuit emulation forms a 
small market, populated with many 
smaller manufacturers with limited re- 
sources, and not every vendor can sup- 
port every processor. 


Bf Future scenarios 

At this time, the 32-bit embedded sys- 
tems marketplace is demanding more in- 
tegrated solutions. Currently, manufac- 
turers such as Motorola are answering 
the demand with specialized chips 
which target specific application areas— 
for example, data communications in 
the case of the 68302. However, the 
day isn't far off when customers will be 
able to specify exactly what they want 
on their chips. When that day comes, 
some of the considerations outlined 
above will be even more important. 
Making sure that operating systems and 
compilers have the necessary extensions 
that make it simple to exploit unique 
chip resources will add to the complex- 
ity of choosing development software, 
and the need to get it right the first 
time will shift the development model 
farther away from emulation and closer 
to simulation. 


Art Parmet, senior factory representative, high-performance processor group, Motorola SPS, Woburn, MA 


COMPUTER DESIGN DECEMBER 1992 101 


ESPECIAL REPORT: 32-BIT MICROCONTROLLERS 


the chip into the virtual protected 
world that a software engineer can 
be productive in.” 


BA choice of operating systems 


One decision 32-bit developers face 
that their narrow-bus counterparts 
generally have an easier time with 
is the choice of an operating system 
(os). As is the case with hardware, 
there are many choices here, too. 
Industry analyst Andrew Allison 
says, “One of the key attributes of a 
realtime executive is that it be ROM- 
able—that is, that it execute out of 
read-only memory, because the typ- 
ical embedded application doesn’t 
have a mass-storage system. This 
requirement obviously places a pre- 
mium on compactness of code, 
which has the serendipitous benefit 
of speeding execution.” Allison also 


notes that the realtime operating 
system can mitigate the impact of 
processor context switching and in- 
terrupt latency on deterministic be- 
havior of the system. 

Among the choices there are some 
old and some new items. One of the 
more familiar is C EXECUTIVE from 
JMI Software Consultants, whose ap- 
plications also run under UNIX for 
development. C EXECUTIVE lets you 
hand-optimize code using assembler 
for context switching, task schedul- 
ing, interrupt handling, and block 
data moves. It has a fully preemp- 
tive, prioritized task scheduler, 
standard and device-driven 1/0, and 
message queues for data transfer. 
For RISC processors, it can fit into 
less than 64 kbytes. 

Accelerated Technology’s (Mobile, 
AL) Nucleus RTX provides a realtime 


ECUTIVE RTOS. 


t Copying takes time 


frames on the interrupt stack. 


stack—the task procedure stack. 


rupt stack. 


substantial. 


Software trick receives patent 


llustrating the tight coupling between silicon and tools that embedded sys- 
tems foster, the u.s. Patent Office has issued a patent to Ju! Software Consult- 
ants’ Susan Wainer for a “trick” used in the company’s i960 version of its C Ex- 


The idea covered by the patent saves 13 instructions and 33 memory accesses 
every time there's a process interrupt with task preemption. It even saves one in- 
struction and 20 memory accesses on interrupts without preemption. 


Wainer’s trick involves “lying” to the processor through the processor state 
flag in the i960's process-controls register. The two states the flag can have 
are executing and interrupted, and normally, the names are apt descriptions 
of the flag’s state. Each user task has Its own procedure stack. The first inter- 
rupt that occurs creates an interrupt record and frame at the top of the inter- 
rupt stack. Succeeding or nested interrupts create additional records and 


This creates a problem when the kernel, processing an interrupt, deter- 
mines that there must be a context switch to a higher priority task. The inter- 
rupt stack will have to be overwritten, so the current interrupt record and 
frame must be copied into a task control block, using up cycles and time. 

jms approach is faster. When a process is executing, C EXECUTIVE lies and 
sets the processor state flag to the interrupted state. Then, when an interrupt 
occurs, the processor creates the interrupt record and frame on the current 


If the interrupt occurs while a user task is executing, the kernel lies again 
and sets the processor state flag to the executing state. Subsequently, if an- 
other interrupt occurs during the processing of the first interrupt, the proces- 
sor switches to the interrupt stack and the kernel leaves the processor state 
flag set to interrupted. All succeeding interrupts create frames on the inter- 


As a consequence of this use of the state flag, when there’s a preemption 
to a higher-priority task, the kernel doesn’t have to copy data from the inter- 
rupt stack, because the user task information is already on the interrupted 
task's procedure stack. The savings, in instructions and memory accesses, is 


There is also a further benefit in saving global registers in local registers dur- 
ing interrupt processing. Normally, the global registers would be saved on the 
stack, using loads and stores. With Jml’s innovation, however, global registers 
can be saved in local task registers, where they will be safely preserved in the 
event of a context switch. 


102 DECEMBER 1992 COMPUTER DESIGN 


multitasking executive for AMD’s mi- 
crocontrollers. Other new develop- 
ments include Ready Systems’ 
(Sunnyvale, cA) Spectra cross-devel- 
opment environment, which cur- 
rently is only available for the 68000 
family. Spectra facilitates debug- 
ging without a hardware target by 
providing a “virtual” software tar- 
get. Spectra updates the company’s 


“Our job is to change 
the hostile physical 
world of the chip into 
the virtual protected 
world that a software 
engineer can be pro- 
ductive in.” 

—Dick Jensen, Applied Microsystems 


VRTX32 kernel with VRTXsa, pro- 
viding a 30-percent improvement in 
time-critical calls. The Spectra tool- 
set is open to third-party tool 
developers. 

At about the same time that 
Ready announced Spectra, Wind 
River Systems (Alameda, CA) intro- 
duced MicroWorks, its development 
environment for the 68000 and 
80960 families, with sparc and 
R3000 support coming. The target 
can be connected to the processor via 
an in-circuit emulator (ICE) cable, or 
more economically by an RS-232 se- 
rial port. 

Integrated Systems’ (Santa Clara, 
CA) pSosystem is an update that in- 
tegrates the company’s psos real- 
time kernel with C, C++ and Ada 
compilers. User options include 
complete UNIX networking, file man- 
agement and graphical interface 
software. The company’s XRAY+ de- 
bugger now handles C++ language 
features. 

When embedded programmers 
coded in assembly language, debug- 
ging was simpler. Optimizing com- 
pilers have changed all that. Com- 
piler optimizations include moving 
invariant expressions outside of 
loops; loop rotation, in which the test 
is placed at the bottom of the loop 
(saving one branch instruction per 
loop iteration); and replacing multi- 
plications with much faster adds 
and shifts. Expressions that can be 
computed are turned into constants, 


and the most frequently used varia- 
bles are kept in internal registers. 

Obviously, closer links between 
the os and the debugging software 
help you understand what your 
debug traces are showing you. In 
one example of closer linking, Ap- 
plied Microsystems and Wind River 
recently got together to let informa- 
tion about data structures, flags and 
semaphores pass between the ker- 
nel and debugger. 

One problem in using source-level 
debuggers and ICEs in 32-bit designs 
is the inability to examine the con- 
tents of processor registers directly 
in realtime. You have to either sin- 
gle-step or look at the entire real- 
time trace buffer and calculate 
changes in register values manually. 
Applied Microsystems has attacked 
this problem with an inference en- 
gine in its XICE source debugger for 
Motorola’s 68330, 68340 and 
68F333 processors. The so-called 
“intelligent trace disassembler” 
builds a model of the processor state 
and modifies it as instructions exe- 
cute. The result is an accurate his- 
tory of hardware register values and 
corresponding instructions at any 
place in the trace. 


| Target integration 


Every time processors get wider 
buses or faster clocks, the engineers 
who design in-circuit emulators get 
a new set of challenges. So far, how- 


For more information about the technologies, products or companies mentioned 
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Advanced RISC Machines 


(408) 399-5195 . ae Circle. 257 
Accelerated Technology 

(205) 661-5770 . Circle. 258 
Adaptec 

(408) 945-8600 Circle. 259 
Advanced Micro Devices 

(800) 292-9263 Circle. 260 
Applied Microsystems 

(206) 882-2000 Circle 261 
Circuit Components 

(602) 967-0624 Circle. 262 
Cypress Semiconductor 

(512) 892-7802 ..... Circle. 263 
DP-Tek 

(316) 687-3000 . Circle 264 
Embedded Performance 

(408) 980-8833 . Circle 265 
Fujitsu Microelectronics 

(408) 456-1000 Circle. 266 
Integrated Device Technology (IDT) 

(408) 492-8631 * Circle. 267 
Integrated Systems 

(408) 980-1500 Circle. 268 
Intel Corporation 

(800) 548-4725 Circle. 269 
JMI Software Consultants 

(215) 628-0840 ‘ Circle. 270 


ever, they haven’t been beaten. 

The Applied Microsystems 
EL3200 supports Intel’s i960 and 
Motorola’s 68000 families. STEP En- 
gineering’s (Sunnyvale, CA) Excell 
and Eclipse emulators support, re- 
spectively, Fujitsu’s SPARClite and 
AMD’s 29200 and 29205 with full Ick. 
In the case of SPARClite, the avail- 
ability of an emulation interface fa- 
cilitates the implementation of an 
in-circuit emulator. 

Also worth noting is that, even 
though it runs at 40 MHz, sTEp’s 
Excell doesn’t buffer the pins of the 
chip, letting the probe run with the 
same timing as the actual chip in the 
target system. 

More economical than full Ick, 
STEP provides a JTAG 29K emulator 
for the 29205 which takes advan- 
tage of the boundary-scan capabili- 
ties of the new AMD chips. Applied 
Microsystems’ low-end CodeTap em- 
ulator supports i960 and 68330 
families. 

Other ICE suppliers include 
Embedded Performance (Santa 
Clara, CA), which provides emula- 
tors for SPARC, MIPS and 29000 chips. 
Its most recent announcement is the 
SYS29K-PUMA for the 205. a 


McKenzie Technology 


(510) 651-2700 Circle 271 
Microtec Research 
(408) 980-1300 Circle 272 


Motorola, Microprocessor and Memory Tech- 
nologies Group 


(512) 891-2037 Circle 273 
Phoenix Technologies 

(617) 551-4000 Circle 274 
Ready Systems 

(408) 736-2600 Circle 275 
S-MOS 

(408) 922-0578 Circle 276 
STEP Engineering 

(408) 733-7837 Circle 277 
TeleSoft International 

(901) 854-5267 Circle 278 


Texas Instruments Semiconductor Group 


(214) 995-6611, ext. 3990 .Circle 279 
VLSI Technology 

(408) 434-7520 Circle 280 
Wind River Systems 

(510) 748-4100 Circle 281 
XLNT Designs 

(619) 487-9320 Circle 282 


Lyte ahead, 64-bit embedded 
systems are on the horizon. IDT 
will probably be first to market with an 
equivalent of the R3051 for the R4000. 
The internal code name is Orion. Ver- 
sion 9 of the SPARC standard, which 
defines a 64-bit architecture, has been 
announced, although no SPARC licensee 
has yet said it’s working on silicon. 

For very powerful embedded sys- 
tems—for example, in medical imag- 
ing—TI's SuperSPARC and Cypress’ 
hyperSPARC are possibilities. By inte- 
grating superscalar IU, FPU and cache 
on pretested modules and providing 
the relatively easy-to-design-to M bus 
as a system interface, these chips sup- 
ply an upscale version of less potent 
monolithic microcomputers. They also 
permit multiprocessing—with up to 
four processors, at least—for applica- 
tions that can take advantage of it. 

In general, 32-bit and wider embed- 
ded systems will maintain their differ- 
ences from more traditional 4- and 
8-bit embedded applications. Code will 
be written in high-level languages by 
engineers who are less familiar with 
fine-grain architectural details than 
they are with the applications for 
which they're coding. At the same time, 
chips will be more highly integrated to 
help insulate developers from hard- 
ware design decisions. Design teams 
will be bigger, and the design effort will 
be a more complex management task. 
And finally, for most companies, time- 
to-market and pricing constraints will 
continue to shrink. 


Sak 


COMPUTER DESIGN DECEMBER 1992 103 


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CIRCLE NO. 53 


| simulator 
integrates off-the-shelf 
subsystems 


Gt 5 aver 


The 171150 Truck Driving Simulator design team from left to right (sitting): Rich DeFouw, software 
program manager; Perry Paus, engineer; Darrell Davey, senior engineer; from left to right (stand- 
ing): John Eisenhardt, chief scientist; Karen LaFond, engineer; John Dibbs, senior engineer; Al 
Berrie, director of engineering. 


F... years ago, FAAC Incorporated (Ann Arbor, MI), a software company in the 
defense industry, saw an opportunity to create its first commercial product. A phone 
call from a former employee sparked the idea of designing a truck driving simulator— 
one realistic enough for trucking companies to use as an alternative to on-the-road 
training. After keeping the idea as a back-burner market research project for a year, 
FAAC decided to pursue a design concept that would eventually become its TT150 Truck 
Driving Simulator. 

While FAAC has a reputation for success in creating training simulators for the 
military, the company was cautious about jumping into the commercial market. “We 
didn’t want to be a defense company telling the commercial world, ‘This is what you 
need,” says Albert Berrie, director of engineering at FAAC. “So we created an industry 
advisory council.” 


' Advisory council provided expertise 


FAAC brought in people from both the trucking industry and academia who were 
involved in driver safety and trucking issues. The council included members from large 
trucking fleets, such as Federal Express, North American Van Lines and Roadway 
Express, as well as the University of Michigan’s Transportation Research Institute. 
“We met with these people and bounced our ideas off them,” says Berrie. “They told us 
what they thought the simulator product should do, and where it fitted into the whole 
training scenario.” 


Jeffrey Child, Senior Editor 


COMPUTER DESIGN DECEMBER 1992 105 


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CIRCLE NO. 54 


INSTANT DATA ACCESS (IDA) 
DIAL (617) 494-8338 DOCUMENT NO. 1037 


Mix & match 1/0 


I DESIGN STRATEGIES: TRANSPORTATION SYSTEMS 


77150 Truck Driving Simulator: how it works 


The 1T150 uses computer- 
generated imagery to provide a fully 
interactive truck driving simulation. 
Fundamentally, the system consists 
of three computers: a VME dual- 
board Motorola Delta system, a Ball 
994 graphics system and an Amiga 
2000 HD desktop system. 


The Ball system generates the im- 
ages on three projectors. It runs ren- 
dering software and processes 
display lists. A 68040 board in the 
Delta system performs all the 
paging of terrain database informa- 
tion, loads polygons and provides 
eyepoint information and vehicle 
position information. The 68040 re- 
ceives realtime data concerning the 
position and orientation of the ve- 
hicle from a RISC 88000 board in 
the Delta. This data is passed to the 
Ball, along with a list of the current 
polygons within the view volume. 


Residing in the Motorola Delta 
system, the RISC 88000-based 
MVME181 board performs several 
duties. It contains a sophisticated 
simulation model of a tractor trailer 
rig, including a full 14° of freedom. 
The 88000 handles height-above- 
terrain (HAT) calculations, keeping 
track of six contact points on the 


road, which approximates 18 
wheels. 


Finally, all the parameters that 
drive the sound system are defined 
through the 88000. When the 
brake is applied, for example, the 
sound system generates an air-re- 
lease sound. 


In the Ball graphics system, soft- 
ware performs rendering processing 
and forms the images out of the 
polygons in the immediate area, 
drawing pictures based on what the 
Motorola boards tell it. The 68040 
board tells the Ball where the truck 
is located and passes it a list of poly- 
gons. The 68040 also controls two 
VMIC V/O cards, one digital and one 
analog, that interface with hard- 
ware in the cab such as the steering 
wheel, gauges, clutch, and gear- 
shift levers. The truck model re- 
sponds to changes in throttle and 
passes new orientation data back 
to the 68040's UNIX system. 


The Motorola Delta system accu- 
mulates scoring information—cur- 
rent speed versus the speed limit, 
for example. At the end of the run, 
this information is processed and 
passed back to the Amiga, where 
the data is graphically represented. 


~ nication requirements. 


Over time, FAAC’s ideas and the 
advisory council’s feedback developed 
into a design strategy. Because the 
company was entering the commer- 
cial market, the driving force behind 
its strategy was cost. “Everything 
we did we did with an eye towards 
minimizing the cost,” says Berrie. 
“We tried to target the cost at 
roughly what it would cost a fleet to 
buy one full truck rig and trailer— 
about $150,000.” 


B Partnership aided process 


With itself as the managing partner, 
FAAC formed a partnership called 
Professional Truckdriving Simula- 
tors. The other partner, Perceptron- 
ics (Woodland Hills, cA), did the me- 
chanical design of the simulator, 
building the cab, the instrument 
panel and the enclosure. In addition 
to overall program management, 
the FAAC team was responsible for 
the computer design, developing the 
software and evaluating, selecting 
and integrating the TT150’s com- 


puter hardware. 

Users of the TT150 sit in a mock- 
up of an actual truck cab. It contains 
a seat, steering wheel, clutch, gear- 
shift lever, and all the gauges found 
in a typical truck. Three large 
graphic displays provide a 180° pan- 
oramic view of the road, along with 
inset images representing two rear- 
view mirrors. Large bass speakers 
in the TT150’s cab create the sound 
and vibration of a truck’s diesel en- 
gine. The TT150 also has an Amiga 
2000 HD computer as an instructor 
station from which driving condi- 
tions can be varied and the driver’s 
performance monitored. 

The most fundamental require- 
ment stipulated by the advisory 
council was that the simulator be- 
have as much like a real driving 
simulation as possible. “You can’t 
create emergency risk-of-death sit- 
uations at a training school or in a 
vehicle,” says Berrie. “The simulator 
gives the instructor the ability to 
create failures in situations that you 


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Return to: CMC, 200 Connecticut Avenue, Norwalk, CT 06856-4990 
(800) 243-3238, fax (203) 857-4075. Bss 


CIRCLE NO. 56 


i DESIGN STRATEGIES: 


TRANSPORTATION SYSTEMS 


At the center of the T7150 Truck Driving Simulator is a mock-up of an actual truck 
cab—complete with seat, steering wheel, clutch, gear-shift lever, and all the gauges 
found in a typical truck. Three large graphic displays provide a 180° panoramic view 
of the road, along with inset images representing two rear-view mirrors. Large bass 
speakers inside the cab create the sound and vibration of a truck’s diesel engine. 


can’t recreate on the road, and to 
evaluate how the driver reacts to 
those situations.” The key to provid- 
ing a realistic, fully interactive driv- 
ing simulation was computer- 
generated imagery. 


i Getting good graphics 


The biggest technical challenge for 
the FAAC engineers was finding and 
integrating a graphics subsystem 
that met their requirements. The 
TT150 required three forward chan- 
nels for the three displays, with two 
channels for the rear-view mirrors. 
A realistic simulation required a sys- 
tem that could process 5,000 polygons 
in a scene at a minimum update rate 
of 15 Hz. At certain critical periods, 
the update speed had to reach 30 Hz. 
Selecting a graphics system that 
met these requirements at an ac- 
ceptable cost proved difficult. 
Several such systems were eval- 
uated by the FAAC engineers, includ- 
ing multiboard products hosted in 
Sun systems and Silicon Graphics 
systems. “The ones that were 
mounted in workstations, to a great 
extent, didn’t have true realtime 
capability,” says Berrie, “so we 
started zeroing in on companies that 
concentrated on graphics and real- 
time simulation, as opposed to work- 
station-based products.” 
Eventually the team chose the 
Ball 994 graphics system made by 
Ball sED (San Diego, CA), an aero- 
space company. One reason FAAC 
liked the system was because of its 


scalability. “We were looking for a 


modular type of system that we | 
could scale up or down based on the | 
horsepower we thought was neces- | 


sary,” says Berrie. For FAAC’s pur- 
poses, the system configuration con- 
sisted of three frame-buffer cards, 
one for each of the channels. Other 
boards included a pixel processor, 
span processor and, depending on 
the polygon load, from one to three 
display-list processors (DLPs). 

The DLPs take a list of polygons 
and sort them. From the polygon 
data, the span processor computes 
which pieces of each polygon belong 
on each span line. The pixel proces- 
sor receives span-line information 
and breaks it down into specific 
pixel data, such as color, luminance 


and chrominance. Pixel information | 


which represents the image dis- 
played on the screen is then stored 
in the frame buffers. Multiple sets of 
these boards may be used to achieve 
more horsepower. 

Choosing the Ball system forced 
some trade-offs on the software side 
of the project. In the final system, 
the FAAC team had to create software 
that hadn’t been planned. Many of 
the graphics systems FAAC con- 


sidered had the capability to per- | 


form key simulation functions. The 
detection of a collision between the 
truck and another object in the 
database, for example, was handled 
directly by many graphics systems. 
Likewise, the height-above-terrain 
(HAT) function was taken care of by 


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CIRCLE NO. 58 


i DESIGN STRATEGIES: 


some graphics systems trans- 
parently. (The HAT function deter- 
mines the location of the physical 
contact point between the tire and 
the polygon it’s driving on.) 

The Ball system, unlike the other 
graphics systems considered, is 
basically only a rendering box. The 
FAAC team, as a result, had to create 
additional software to define HAT 
and collision databases, and then 
had to store those databases on 
other hardware. The group also had 
to develop code to perform sorts and 
searches, as well as algorithms to 
provide the output. 


B VME for flexibility 


Early in the design cycle, the FAAC 
team had to choose a main computer 
engine upon which to run the simu- 
lation. It decided on VME boards with 
Motorola microprocessors. “We 
didn’t care for the memory address- 
ing of the Intel chips,” remarks 
senior engineer John Dibbs. “We 
preferred the linear address space 
that you get from the Motorola ar- 
chitecture. As for the choice of VME, 
that fitted our strategy of going for 
off-the-shelf hardware. We thought 
that VME would give us a wide range 
of third-party vendors to provide 
what we needed. Also, the whole 
development cycle supported the ap- 
proach of keeping options open.” 

The designers settled on an archi- 
tecture consisting of a pair of single- 
board computers, a 68040-based 
MVME167 board and a RISC 88000- 
based MVME181 board. The 68040 
board, running UNIX, acted as the 
development environment and con- 
trolled peripheral /o in the TT150 
system. The RISC board, running the 
psos realtime operating system, pro- 
vided the power needed to drive all 
the autonomous vehicle models, and 
to run the truck model itself. By 
using SBCs and the vME architecture, 
FAAC gave itself a path to easily up- 
grade to higher-performance boards 
as they become available. 


B RISC muscle critical 


Among the reasons for including a 
RISC processor in the TT150 was the 
need to keep high-frequency models 
numerically stable. Models of the 
trailer hitch and suspension sys- 
tems are both examples of high- 
frequency models. In a dynamic 
simulation, loops can occur in the 
simulation in the space of microsec- 
onds. During that interval, certain 
assumptions are made about which 
variables remain constant. Some 


TRANSPORTATION SYSTEMS 


weights, for example, are defined 
and integrated. In a dynamic system 
that is oscillating, problems can 
occur if the integration interval is 
too large. In such cases, the integra- 
tion can result in a value that’s un- 
realistic. This can create a numeri- 
cal instability, causing the system to 
oscillate out of control. 

“The best way to resolve this in a 
given model,” says Berrie, “is to 


shrink your integration interval | 


down to a small enough piece— 
small enough so that you can’t ex- 
trapolate far into the future with 
bad information. We were concerned 
that we would have to run a vehicle 
model at a very high-frequency 
rate—30 Hz or higher—rather than 
the 15 Hz of the display system. We 
wanted to make sure we had suffi- 
cient horsepower and capability in a 
RISC realtime computer to handle 
that. That steered us toward the 
RISC 88000 processor and psos.” 


For its part, the 68040-based | 


board performed as the overall sys- 
tem executive for the TT150. The 
68040 handles the realtime paging 
function that pulls terrain database 
information off the disk and delivers 
it to the Ball system. Through a 
shared memory arrangement, the 


88000 and the 68040 pass informa- | 


tion back and forth. 


Bl Lessons learned 


The TT150 Truck Driving Simulator | 


design provided the FAAC design 
team with some insights into the 
importance of cost for commercial 
designs. “We were attempting to 
avoid new development, new pro- 
ducts, new concepts,” says Berrie. 
“We wanted to take off-the-shelf, 
currently available pieces of hard- 
ware and integrate them into a new 
application. Our market research 
told us that if we built a system that 
cost $300,000, the market just 
wasn’t going to support it. We 
worked very hard to keep the price 
down, and we identified the com- 


ponents and computers that would | 


help us achieve our target cost.” 
Because of the graphics system, 
the final cost of the TT150 was 
$230,000. “At first, the graphics sys- 
tem was the only component not 
available off-the-shelf,” adds Berrie. 
“We had to settle on a price-perform- 
ance point that we needed for our 
product. In the end, that made the 
TT150 commercially acceptable.” & 


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CALL FOR PAPERS: 


THE ATTENDEES 


EE [rcs from other industry events because it focuses on 


providing solutions for a variety of embedded computer 

applications rather than focusing on technology alone or 
products alone. Developing these applications and finding the best 
solutions brings into play single-chip microprocessor and 
microcontroller implementations; custom and semicustom board 
designs; standard bus-based single-board computers and peripheral 
boards; operating systems, real-time kernels and compilers; 
development systems and debugging tools; embedded PCs, 
embedded workstations and even embedded microcomputers. 

ECC attendees are intimately involved in the design, 
development and integration of a broad range of products and 
systems based on embedded computers. 

ECC attendees are working in all major industries, where they 
are designing, developing and building a full spectrum of products 
and systems. 

¢ In the computer industry, developing workstations and larger 
computers and making decisions about proprietary buses, open 
architecture buses or bus-less approaches. 

¢ In process control and automation, developing systems for 
motor control, process measurement and control, machine 
vision, robotics and manufacturing automation, traffic control, 
etc. 

¢ In communications, developing systems for use in cellular 
communications, PBXs, multiplexers, local area networks and 
wide area networks, etc. 

¢ In the military/aerospace and avionics industries, building 
equipment and systems for communications, command and 
control (C3), weapons guidance and control, simulation, air- 
borne and ground-based flight-control systems, etc. 

¢ In the test, measurement and instrumentation industry, where 
equipment and systems are being built for product testing, 
maintenance and service applications, diagnostics (including 
medical), resource exploration, etc. 

¢ Research and development, where scientists and engineers are 
designing equipment and systems for data acquisition, analysis 
and simulation that range from benchtop systems to space 
stations. 


APPLICATIONS MARE THE DIFFERENCE AT ECC 


THE PROGRAM 


*s technical program has been designed to provide 
E fi ffanences with the practical information they need to 

incorporate embedded computers in an end product or 
subsystem. These embedded computers can take the form of 
dedicated microcontrollers; sophisticated 32-bit CISC or RISC 
processors; off-the-shelf or customized SBCs; standalone SBCs; 
standard bus-based subsystems; or OEM workstation, desktop or 
industrial computer platforms. 

While the Technical Program Committee will entertain proposals 
for presentations covering a broad range of embedded computer 
approaches, special consideration will be given to proposals 
dealing with the following major areas of concern: 


OYOTEM ARCHITECTURES 


Presentations in this category will deal with interprocessor and 
memory architectures, custom and semicustom system 
implementations, and loosely and tightly coupled software and 
hardware models. This section will include a discussion of chip sets 
for “standard-architecture” machines such as the X86-, SPARC- or 
MIPs-based workstations and the features that make them suited, or 
unsuited, to embedded applications. Some other areas of interest 
are: 

« PCs (80X86, P5) in embedded applications 

« RISC architectures (Alpha, HP-PA, MIPS, SPARC, 88K) in 

embedded applications 

¢ Integrating processor, memory and I/O on stand alone SBCs 

¢ Memory architectures with or without cache 

« Symmetrical and asymmetrical multiprocessing 

* Live-insertion, fault-tolerant, high-availability computing 


INTERFACES AND STANDARDS 


This track will deal with local on-board interfaces, addressing 
issues such as architectural considerations, transceiver 
considerations (cost, power, space, time-to-market) and 
implementations, current and emerging standards such as PCI and 
PCMCIA as well as more conventional mezzanine-I/O buses such 
as IndustryPacks, SBus, MX bus and others. Particular areas of 
concern include: 

* Standard mezzanine/daughter boards 

* SBus, TURBOchannel and other workstation I/O buses 

* 80X86 (P5) peripheral interfaces 

¢ Networking interfaces such as Ethernet, ATM and SONET 

* Peripheral interfaces such as SCSI, HiPPI, and FiberChannel 

* MCM standards and interprocessor module buses 


a Embedded Computer Conference 
April 14-16 1993 © Santa Clara Convention Center © Santa Clara, California 


EMBEDDID COMPLTER CONFERENC [ SSR 225 A ESTED LED ELD LAE LE EE LENA N TE ETI, 


Se) Seb 6, Si oO SD 8 


INTERCONNECT RACHITECTURES 


The approaches to interconnecting board-level subsystems are 
undergoing a revolution, including the development of new 
standards such as PC/104, SCI (Scalable Computer Interface) 
and Futurebus+, as well as major changes and enhancements to 
such well-established standards such as VME and Multibus II. 
In addition, there are many other approaches vying for the 
embedded market such as ESP (Extra Small Package), various STD 
approaches, G64 and others. Rapidly changing semiconductor 
technology is forcing changes in bus and interface technology 
which are reflected in: 

* VMEbus, Multibus, Futurebus+, STD/STD32 

¢ Custom and semicustom implementations 

* High-performance backplanes 

¢ Bridges and intercrate communications 


SOFTWARE AND DEVELOPMENT TOOLS 


Because embedded computer applications involve real-time 
processing, the major software focus of ECC will be real-time 
issues. Special emphasis will be given to multiprocessing in real- 
time using both traditional and Windows-based operating systems. 
Also of interest to attendees are: 

* Real-time OS and kernels 

* Real-time DOS 

* Windows for embedded and real-time applications 

* Multiprocessing with DOS and other real-time OSs 

¢ High-performance optimized compilation 

« POSIX and POSIX compatibility 

* Communications protocols/standards 

¢ Ada in military and nonmilitary applications 
Proposals will be considered for presentations on any of the above 
topics, as well as on any other topics related to the design, 
programming and application of embedded computer products, 
subsystems or systems. 


HOW YOU CAN PARTICIPATE 


ou may participate in the ECC Technical Program by submitting 
a proposal for either a one-hour lecture-type presentation, a 20- 

minute application-focused paper, or a longer tutorial. Please 
submit your proposal no later than November 20, 1992. 

The proposal should be no longer than one page and consist of 
a short abstract that summarizes the content and goals of the 
presentation, and a brief outline of the major topics covered by the 
presentation. Presenters must be technically qualified and able to 
answer questions from attendees. A short biography of the 
presenter, detailing his or her technical background and 
accomplishments must accompany the proposal. 


COMPUTER "7 


A FOCUS ON SOLUTIONS ——_— 


THE FORMAT 


: combination of one-hour presentations, application-focused 


multi-paper sessions and tutorials will address a broad range 
of topics of importance to engineers and engineering managers 
designing both the hardware and software for embedded computers 
and subsystems. 
¢ Tutorials are extended presentations intended to provide 
attendees with an in-depth understanding of core technologies 
used in embedded computers. 

Individual presentations are focused on various aspects of 

applying new or emerging technologies and products to solving 

specific problems in designing products or subsystems using 
embedded computers. Special consideration will be given to 
presentations that emphasize make-or-buy trade-offs in specific 
applications. 

« Multipaper sessions consist of several shorter papers that focus 
on the implementation of embedded computing in specific 
application areas, including: 

Medical instrumentation 

Vehicular traffic control 

Signal processing/data acquisition/DSP 
Automated vehicles 

Machine control 

Graphics 

Low-power and portable applications 
Imaging 

Visual inspection 

Virtual reality 

Military C31 

Communications 

Peripheral interface and control 
Process control 

Laboratory automation 

Multimedia 

Networking 


Acceptance of proposed presentations will be made by 
December 2, 1992. A complete copy of the presentation, including 
all visuals and graphics, for publication in the Conference 
Proceedings must be provided by March 1, 1993. Presentations 
given at ECC will be published in the Proceedings and copyright 
shall be assigned to Computer Design/PennWell Publishing 
Company. 


1993 INTERNATIONAL 
TECHNICAL CONFERENCE SERIES 


COMPUTER DESIGN ¢ One Technology Park Drive * P.O. Box 990 * Westford, MA 01886 


Tel: 508-392-2124 ¢ 800-223-4259 « Fax: 508-692-7780 


CIRCLE NO. 60 


Imagine Getting VME Performance ... 
... at Half the Size and Cost. 


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ZT 8911 Scalable Processor Board 


Imagine No More. 


Intel 486 Performance 

Two new 486 industrial computers from Ziatech offer 
performance choices ranging from the 25 MHz 486SX to the 
66 MHz 486DX2 in a very embeddable format. 


PC Software, Multiprocessing Control 
These high speed processors will run any PC operating 

system you need - MS-DOS, OS/2, QNX, UNIX, and more. 

And the STD 32 format provides something a PC or VME solution 
can’t give you — multiprocessing capability that lets up to seven 
DOS-based processors share peripherals in a single system. 


42-bit, Local Bus Video 

Optional SuperVGA local bus video on the ZT 8902 SBC runs 
high resolution graphics at 486 CPU speed without using an 
extra I/O slot or any backplane bandwidth. 


SO 


The Embedded Computer 
CIRCLE NO. 61 


Small, Industrial Format 

Ziatech’s 486 computers provide all of the above and 
more in the compact 4.5- by 6.5-inch STD 32 format, the 
embedded computer that doesn’t waste your money on 
board space and features you don’t need. 


Free Data Book 
Call or Fax today for Ziatech’s brand 


bd 


new STD 32 technical data book, 

which includes full specifications on 
our new 486 offerings and the rest of 
our industrial computer product line. 


Phone: 805-541-0488 
FAX: 805-541-5088 


<|_Z1arecH 


CORPORATION 


©Copyright 1992 Ziatech Corporation. All rights reserved. Product names 
of other companies may be trademarks of those companies. 


PRODUCT FOCUS: STD BUS CPUs 
COMPUTERS AND SUBSYSTEMS 


= 


STD Bus CPUs 
focus on 
solutions 


Jeffrey Child, Senior Editor 


nlike VME, which has Mo- 
U torola supporting it, or 
Multi-bus II, which is backed 
by Intel, STD Bus may suffer from 
not having a major semiconductor 
manufacturer behind it. But in re- 
ality, STD has a strong position as 
the low-cost workhorse bus for em- 
bedded control. STD Bus cards offer 
rugged hardware in a 4.5 x 6.5-in. 
form factor, as well as access to 
many off-the-shelf software devel- 
opment tools. 
To keep the cost of their products 
low, STD cpU board makers use the 


inexpensive microprocessors and | 


chip sets targeted for the pc market, 
where extreme price pressures and 
high volumes have had a favorable 


impact on the price and availability | 


of components. Even more impor- 
tant, the exploding notebook pc mar- 
ket is driving the need for ever 
tighter integration of electronics, a 
trend that fits nicely with the re- 
quirements of a small-form-factor 
bus such as STD. 

The newest STD cPU boards reflect 
aggressive efforts to leverage these 
hardware developments in the PC 
world. The current selection of sTD 
Bus cpus ranges from highly inte- 
grated, single-board computers to 
high-performance engines for han- 
dling the central computing tasks of 
a multiboard system. Among these 
are six new 486-based boards. 


Bl Trend toward solutions 
If there’s a trend in stp boards these 
days, it’s toward a focus on solutions 


for the customer. This trend covers | 
several areas, including support for 
multiprocessing, special /O require- 
ments, add-on modules, and future 
performance upgrade paths. 

While many STD cPU board makers 
are pushing for increased perfor- 
mance, there’s disagreement among 
these vendors over what future STD 
Bus performance should look like. 
Ziatech (San Obispo, CA) and a hand- 
ful of other vendors are focused on 
STD 32, the 32-bit extension of the STD 
Bus standard. They argue that the | 
bus should continue to act as a trans- 
fer medium, and so 32-bit access to 
memory or disk interfaces should oc- 
cur over the bus. 

Most of the STD Bus board makers | 
take a different view, however. Their | 
approach, and the approach sup- 
ported by the stp Manufacturers 
Group, is to put all the computing 
power on the cpu card. Technology 
advances have let designers inte- 
grate a complete SBC, with ample 
memory and peripheral functions, 
onto a single stp Bus card. Such an 
approach relegates STD to acting es- 
sentially as an /O bus channel. But, 
at speeds of 5 or 8 MHz, and using 
8- or 16-bit specifications, STD is 
more than fast enough as an /O bus. | 

Despite contrasting opinions over 
the need for a 32-bit stp Bus, some 
STD users take comfort in the fact 
that stp 32 provides an avenue for | 
future performance upgrades and 
32-bit multitasking—whether they 
need these capabilities or not. 

Designers at Hettinga Equipment 


STD 32 CPU boards 
from Ziatech pro- 
vided a solution for 
Hettinga Equip- 
ment when it 
needed a multista- 
tion injection mold- 
ing machine. The 
system uses a PC as 
a master to control 
Ziatech’s 8901 
boards as slaves. 
These boards 
(lower right) per- 
form the realtime 
control and data ac- 
quisition functions 
of the system. 


(Des Moines, IA), an OEM of injection 
molding machinery, used STD 32 CPU 
boards from Ziatech to control its 
latest multistation machine. While 
most molding machines can mount 
only one tool at a time, Hettinga’s is 
unique in that it has up to six mold- 
ing stations, all serviced by the same 
injection unit. This lets up to six 
different parts be molded on a single 
machine. 

Hettinga’s system uses an IBM PC 
as a master computer, This PC is 
connected to one or more Ziatech 
8901 stp 32 cpu boards. These boards 
in turn run the realtime control and 
data acquisition functions of the sys- 
tem. Specifically, the 8901 works with 
STD 32 A-D interfaces and an 8-bit 
PAMUX card to provide standard 1/o 
channels to the control process. A 


| flat-panel display may be added us- 


ing a Ziatech video interface. 

Although Hettinga’s machine de- 
sign doesn’t take advantage of the 
32-bit features of the stp 32 8901 
card, Richard Osborne, software 
project leader at Hettinga, plans to 
use the multitasking capabilities of 
sTpD 32 in the future. “We have some 
applications in preliminary design in 
which we have a multitasking type 
of control system,” says Osborne. 
“We want those processors to share 
resources, such as the video card 
and a serial port. On the 8-bit stp 
Bus you could have two 386 cards, 
each with its own video, but you’d 
need to have two monitors. To me, 
that’s one case where STD 32 makes 
a difference.” 


COMPUTER DESIGN DECEMBER 1992 115 


EPRODUCT FOCUS: STD BUS CPUs 


= 
38 

a i — —_ o- 

eats S 3 3 SES 

se B cs ts 

_ oso— 2 F-} } £e 

= Za ou =e — — Cs 
=] = =o = = = 3 
=] a Qe o 4 o =e 
= ) Goa =o c c — 


BAS-52 8031/ 11.05 no 8-16k 8-16k ao 
32/52 
BIB-52 8031/ 14.4 no 32k-128k 256k — 


32/52 


ANC-7850 8032 11 no 32k 32k 1 
ANC-7852 8052 11 yes 32k 32k 1 
BASIC 


t 

So 

a 
of 
SMe: a] 
= 

Ee o 
ss 2 
Se = 


Advanced Micro Systems 2 Townsend West, Nashua, NH 03063 (603) 882-1447 


Intel BASIC 48 general 

purpose |/0 
modified 48-144 
Intel BASIC 


Antona 1643 1/2 Westwood Blvd, W Los Angeles, CA 90024 (310) 473-8995 


no 2 8-bit parallel; 


1 RS-232C serial; 


1 serial printer 


BASIC 2 8-bit parallel; 


1 RS-232C serial; 


1 serial printer 


Price 


$329- 


$450 


$320- 


$495 


$195 


$285 


Comments 


Circle 301 


RS-232, printer port 
RS-232; RS-485; optional 12-bit 
A-D 

Circle 302 
Stand-alone or STD Bus 
Stand-alone or STD Bus; on-board 


PROM programmer; real-time 
clock 


8650 800186 16 no 256k 256k 


8660R 800186 12.5 no 64kM 256k 


ACS-09 6809 Gs no 40k 40k 


ACS-685BC 68008 8 no 1M 1M 


DuraSys Box 814, Dover, NH 03820 (603) 742-7363 


ESC 10809 6809 1,2 no 48k 48k — 
ESC 10812 6502 Tye no CMOS EPROM — 
to 48k to 48k 


STD-65F11 R65F11 Hee no 64k 16k — 


Forth card 


116 DECEMBER 1992 COMPUTER DESIGN 


18-bit 


18-bit 


18-bit 


18-bit 


— 4 8-bit parallel, 
2 RS-232 

_ 4 8-bit parallel, 
2 RS-232 


Datricon 31069 Genstar Rd, Hayward, CA 94544 (510) 471-9717 


ROM 2 parallel, 
monitor 1 serial 


ROM 2 parallel, 
monitor 1 serial 


HiTech Equipment 9400 Activity Rd, Ste 1, San Diego, CA 92126 (619) 566-1892 


os 3 RS-232, 
2 parallel 


Cubit Division, Proteus Industries 340 Pioneer Way, Mountain View, CA 94041 (415) 962-8237 


$595 


$775 


$215 


$545 


$295 


$295 


$299- 


$349 


C-Matic Systems Ltd 2 Millbrook Business Park, Crowborough, E Sussex TN6 3J2 44-892-665688 Circle 303 
STD 1804 280 4,6 no 64k 64k — — PIO/SIO $290 
STD 1878 68030 12 no 16-32M 64k _ _ _ $1,650 
Computer Dynamics 107 S Main St, Greer, SC 29650 (803) 877-8700 Circle 304 
CPU-XT 8088/V20 5,8 optional 640k 256k 2 DOS 2 RS-232; $995 100 PC/XT compatible; directly 
1 parallel drives flat-panel displays or CRTs 
CPU-AT 806286 12,16, optional 4M 256k 2 DOS 2 RS-232: $1,995 100 PC/AT compatible; directly 
2 1 parallel drives flat-panel displays or CRTs 
printer 


Circle 305 


C-Engine S/W, watchdog timer, 16- 
bit STD Bus 


12-bit A-D; —40° - +85°C; NAVMAT 
P-9492 vibration spec; C-Engine 
S/W; battery-backed RAM/clock 


Circle 306 


Circle 307 


4 timers; power-fail detect; inter- 
rupt generation; CMOS RAM 
backup 


Same as above 


Circle 308 


2 E 
Sy cal a ae ee 2 
= Z sy =e - = s eg E 5 o =e 
=] > je =s : os a. 3 e 
= 8 Be £8 Fs a Se g = -s 
JF Microsystems 3641 Frontier Rd, Pasco, WA 99301-9619 (800) 532-2737 Circle 309 
4188 8088 5 no 16k 32k _ _ 4 parallel $400 1/0 processor 
8759 8088 5,8 OPT 8087. — 32k 18-bit _- = $500 STD Bus master 
Magnon Engineering 8739 Lion St, Cucumonga, CA 91730 (714) 466-0199 Circle 310 
13000 68B09 8 no Step motor 1 IEEE, $400 For step motor applications 
controller 2 RS-232 
1-11 axis 
Matrix 1203 New Hope Rd, Raleigh, NC 27610 (800) 848-2330 Circle 311 
MF9B 6809 2 no 64k 32k _ 0S-9 2 serial $305 3 programmable counter/timers 
SP9B 6809 2 no 80k 32k — 0S-9 1 serial $255 configuration register & software 
controlled memory mapping 
Micro-Aide 685 Arrow Grand Cir, Covina, CA 91722 (818) 915-5502 Circle 312 
80-0046 v40 8/10 no 1M 512k 1 8-bit DOS 1 printer, $375 Battery-backed calander/clock and 
2 serial CMOS RAM; 5 32-pin sockets for 
memory; power-fail detect 
80-0386 386SX 16, 20 no 8M 512k 4 8/16-bit DOS 1 printer, $795 battery-backed calander/clock and 
2 serial CMOS RAM; iSBX expansion 


Micro-Link Products Div. 401 Pennsylvania Pkwy, Ste 205, Indianapolis, IN 46280-1385 (800) 428-6155 Circle 313 


STD224 68020 12,20 6888 1-16M 1M local 0S-9, 32-bit _ 
PDOS local 
STD247 Z80 3.6 no 64k 32k - _ 1 RS-232 _ 
Micro/sys 3447 Ocean View Blvd, Glendale, CA 91208 (818) 244-4600 Circle 314 
SB8386 80386SX 16,20, 80387SX 8M 1.8M 48-bit, RUN.EXE, 2 serial, $845 Complete 386AT on card; VGA, 
25 4 16-bit DOS, 1 printer, IDE drive and STD80/MPX options 
Windows, iSBX 
os/2 
SB8486 CX486SLC 25 80387SX 8M 1.8M 48-bit, RUN.EXE, 2 serial, $995 Complete 486AT w/1-kbyte cache 
4 16-bit DOS, 1 printer, on card; VGA, IDE drive, and op- 
Windows, OS/2  iSBX tions 
Microcomputer Systems 1814 Ryder Dr, Baton Rouge, LA 70808 (504) 769-2154 Circle 315 
| MSI-C988 v20 5.0 no 64k 64k — _ 2 serial, $395 Real-time clock; 3 16-bit timers; 
3 digital, interrupt controller; battery- 
1 analog backup RAM; 10-bit analog input; 
32 digital I/Os 
| MSI-CZ82 Z80A 4 no 8k 8k — _ 2 serial $285 Counter-timer clock 
Miille Applied Research 1730 S Richey, Pasadena, TX 77502 (800) 729-0818 Circle 316 
127-031-0 6809 12 no 8-32k 8-32k _ _ 2 serial, $410 3 16-bit counter timers; watchdog 
16 digital I/Os timer; power-fail detect 
127-031-1 6809 1,2 no 8-32k 8-32k _ — 2 serial, $595 
16 digital I/Os, 
16 analog IN 


COMPUTER DESIGN DECEMBER 1992 117 


PRODUCT FOCUS: STD BUS CPUs 


Model 

CPU(s) 

CPU clock 
speed (MHz) 
Math 
coprocessor 
RAM (bytes) 
ROM (bytes) 
DMA channels 
(no. and witdth) 
Operating 
system support 
1/0 ports 


Mitchell Electronics P.O. Box 2626, 180B Mill St, Athens, OH 45701 (614) 594-8532 


M/E 200 280 2.5, no 16/32k 48k EPROM— Forth 2 serial, 
46 1 IEEE 488 
CPU816 650816 = 4,8 no 8-128k 48k = Forth 2 serial, 
2 8-bit parallel, 
12 bit A-D 
Mizar 2410 Luna Rd, Carrollton, TX 75006 (214) 277-4600 
MZ77851 280 25,4 no 1-2k 8k _ — 3 8-bit OUT, 
2 8-bit IN 
MZ77855 780 25,4 no 256k 4k — — _ 


Octagon Systems 6510 W 91st Ave, Westminster, CO 80030 (303) 430-1500 


7100 64180 6 none 32k 8-32k — STD BASIC II 8 analog IN, 
1 analog OUT, 
38 digital I/Os 
9600 V25 8 no 32k 32-128k — STD BASIC II 24 digital I/Os 
Pro-Log 2555 Garden Rd, Monterey, CA 93940 (800) 538-9570 
7874 486SX/DX 25,33 in CPU (DX) 16M 512k 2aw DOS, 2 serial, 
Windows, 1 parallel 
0S/2, QNX 
7873 386SX 20,25 387 8M 512k 2 DOS, 2 serial, 
Windows, 1 parallel 
0S/2, QNX 


Quasitronics 211 Vandale Dr, Houston, PA 15342 (412) 745-2663 


CPU-Z80 280 2.5 no 8k 8k — CP/M _ 


R.L.C. Enterprises 4800 Templeton Rd, Atascadero, CA 93422 (805) 466-9717 


TSBC-C186 800186 10,12.5, 800187 256k 256k 2 — 2 RS-232 
16 
SBIO-186 80186/ 8, 10, no 256k 128k 2 — 2 RS-232/ 
800186 12.5, 16 RS-422, 
32 parallel I/Os 
Robotrol 925 W San Martin Ave, San Martin, CA 95046 (408) 683-2000 
RSD7832 UP1I42 12 no 32k 64k _ _— 18-bit 
(8051) parallel, 
1 serial 
RSD7808 Z80 4 no 64k 64k — — 20 parallel, 
2 serial 


118 DECEMBER 1992 COMPUTER DESIGN 


Zz 
i 
= 
8 — 
oa ra) 
Circle 317 
$350 IEEE 488 talker/listener controller 
interrupt support for GPIB; 
portable battery-backed RAM; 
cal/clock option 
$450 8 channel A-D; flex memory map- 
ping, 6502 opcode compatible, 
batt- backed RAM, cal/clock option 
Circle 318 
$375- 
$475 
$415- 4 counter/timers 
$435 
Circle 319 
$445 
$595 
Circle 320 
$2,495 Multiprocessor support; CPUs per 
system; disk interface; VGA 
$1,895 Same as above 
Circle 321 
$196 Single +5-V power required; DMA 
control 
Circle 322 
$675 16-bit stand-alone or STD opera- 
(10MHz, — tion; 6 16-bit counter timers; flash 
no cO-pro- memory 
cessor) 
$555 Real-time clock; Opto-22 inter- 
(8MHz) face; RS-422 drivers on RS-232 
ports 
Circle 323 
$595 Intelligent analog 1/0; 16 analog 
IN; 2 analog OUT 
$245 Master/slave; 16-input vectored in- 


terrupt 


cy = a 
xz 7) 2 
oF ” > 
o o 
= CH so = = 
o 2 o se = 
3 = — i 4 = = 
a aa 2s 
= Oo Oa ro) c 


ROM (bytes) 


DMA channels 
(no. and witdth) 


system support 


Operating 


Systek 415 N Quay St, Ste 6, Kennewick, WA 99336 (509) 735-1200 


8825 V25 5, 8, no 512k 
10 

8850 V50 8, 10, 8087 512k 
12 


512k 


256k 


28-bit 


3 16-bit 


MS-DOS 


MS-DOS 


Versalogic 3888 Stewart Rd, Eugene, OR 97402 (800) 824-3163 


VL-186-1 800186 16 no 1M 


VL-188 800188 5,8,10 no 512k 


1/0 ports 


8 analog IN, 

2 analog OUT, 
22 digital, 

2 serial RS-232, 
iSBX 


2 RS-232, 
1 RS-485, 
1 Centronics 


1M 


512k 


2 16-bit 


2 16-bit 


DOS 


WinSystems 715 Stadium Dr, Arlington, TX 76011 (817) 274-7553 


MCM-SX386  80386SX 16,25, 80387SX 4M 

MCM-486DX  80486DX 33,50, in CPU 8M 
66 

MCM-486SLC 80486SLC 25,33 80387SX 4M 


XYZ Electronics 4700 N 600 W, McCordsville, IN 46055 (317) 335-2128 


CPU68k16 68000 16 no 3M 


SB-68k16 68000 16 no 750k 


Ziatech 3433 Roberto Ct, San Luis Obispo, CA 93401 (805) 541-0488 


278902 486SX/ 25,33, in CPU 4-8M 
DX/DX2 50, 66 

278911 486DX/ 33,66 in CPU 4-32M 
DX2 


512k 


128k 


512k 


3M 


1M 


1-2M 


2M 


4 16-bit, 
48-bit 


4 16-bit, 


48-bit 


4 16-bit, 
48-bit 


2 


DOS, QNX, 
0S/2 


DOS, QNX, 
0S/2 


DOS, QNX, 
0S/2 


OS-9/68000 


OS-9/68000 


in ROM 


MS-DOS, 
08/2, 
UNIX, QNX, 
Windows 


MS-DOS, 
0s/2, 
UNIX, 
QNX, 
Windows 


12 parallel, 
1 RS-232, 
1 RS232/422 


16 lines parallel, 


1 RS-232/422 


2 RS-232/ 
422/485, 
1 parallel 


2 RS-232, 
printer 


2 RS-232/422/ 
485, 1 printer 


2 RS-232/RS42 
1 SCSI-compa- 
tible, 1 parallel 


2 RS-232/422, 
1 SCSI-compati 
1 parallel 


2 serial, 
3 parallel, 
1 Centronics 


2 serial, 
3 parallel, 
1 Centronics 


Zwick Systems 17 Fitzgerald Rd, Ste 104, Nepean, Ontario, k2H 9G1, 613-726-1377 


ZSTD-100 284013 4,5, no 512k 
(280) 8, 10 

ZSTD-110 284013 4,5 no 512k 
(280) 8, 10 


512k 


512k 


2 RS-232C 


16 parallel I/Os, 


2 RS-232C 


2 
i 
= 
s = 
a 8 
Circle 324 
$395 Master/slave for multiprocessing; 
watchdog timer; clock/calendar 
$575 Multi-master; watchdog timer; 
clock/calendar 
Circle 325 
$645 STD32; DOS-compatible; hard- 
ware; multiasking; RT embedded 
DOS (trade-mark) 
$325 Opto-22 compatible parallel port 
Circle 326 
$850 PC/104 expansion; floppy cntrl; 
keyboard cntrl; IDE interface; op- 
tional —40° to +85° C operation 
$1,995 iSBX expansion keyboard control- 
ler 
$995 PC/104 expansion; floppy cntrl; 
keyboard cntrl; IDE interface 
Circle 326 
2, $495 Includes real-time clock & battery. 


(no RAM/ All RAM can be battery backed. 
ROM) 


$995 Same as CPU68k16 plus the 
ble, ROMed operating system; non- 
volatile RAMDISk and ROMDISk; 
C compiler; screen editor 


Circle 327 
$1,850  STD32; optional local bus video 
module 


$3,350 Norton index of 103.5; replaceable 
CPU module; full 32-bit backplane 


transfers; STD32 multiprocessing 


Circle 328 


$529 Dual MMU; counter-timer clock; 
watchdog timer; wait-state gener- 


ator; debug monitor 


$589 Same as above 


COMPUTER DESIGN DECEMBER 1992 119 


BPRODUCT FOCUS: STD BUS CPUs 


COMPUTERS AND SUBSYSTEMS 


Ziatech’s latest single-board stp 
32 computer is the ZT 8902, a 486- 
based board with high-speed local 


bus video. The 8902 is available with | 
a choice of Intel 486 processor op- | 


The MCM-SX386 is | 
the first STD CPU 
board to use PC/104 
as a mezzanine bus. 
Offering a choice of 
expansion solu- 
tions, the board pro- 
vides a common 
computer core to 
which you can add 
off-the-shelf or cus- 
tom-designed 
PC/104 expansion 
modules. Based on 

a 33-MHz 386SX mi- 
croprocessor, the 
MCM-SX386 has up 
to 4 Mbytes of on- 
board RAM. 


tions. These range from the 25-MHz 
486SxX to the 66-MHz 486DX2. Local | 
bus 32-bit Super vGA capability is | 
offered on a plug-in module. Accord- 
ing to spokespeople for Ziatech, this | 


video module lets the ZT 8902 run 
high-resolution graphics faster than 


| most high-end pcs. The module oper- 
| ates at 25 or 33 MHz, increasing 


video performance up to 70 percent 
over 16-bit boards that operate at the 
ISA bus speed of 8 MHz. 

Together, the ZT 8902 and the lo- 
cal bus video module occupy a single 
slot in an STD 32 card cage. By off- 
loading the video function, the mod- 


| ule helps prevent bottlenecks on the 
| STD 32 bus. The board also features 


1 Mbyte of flash memory, up to 8 
Mbytes of DRAM, two serial ports, a 
printer port, 24 channels of indus- 
trial digital vo, and extra coun- 
ter/timers. 


B Beat ‘em or join ‘em 

As STD Bus CPU board vendors move 
to a solutions-oriented strategy, 
they're finding that some embedded 
control solutions compete for the 
same types of applications. In re- 
sponse, some vendors have quite 


Our new IBM PC-AT compatible 
single board computer supports both the 
386SX and any 486 processor. It means that your 
products can be truly upgradeable without having 
to stock a multitude of incompatible boards with 

different chipsets, BIOS and connectors. 


We offer outstanding reliability for the most 
demanding applications. Only the highest quality 
components are used from reputable suppliers so 
every batch meets our same high standards. Our 
designs use the latest highly integrated chipsets for 


the highest performance and best PC compatibility. 


Our products are manufactured, designed and 
supported in the USA and Britain and have been 
used for many years in the harshest environments 
by the military, industrial and commercial users. 


120 DECEMBER 1992 COMPUTER DESIGN 


6DX2-50/66MHz ¢ 486DX-33/50MHz ¢ 486SX-20/25MHz * 386SX-25/33/40MHz * 486D 


Features Include: 


¢ Supports any 386SX/486 processor up to a true 50 MHz. 


¢ Flash EPROM for users upgradeable BIOS and 
storage of custom information such as serial 
numbers or company name. 


Frequency synthesizer — replaces 
crystals and oscillators for 
improved reliability. 


Guard banding of 
clock signals for 
highest func- 
tional reliabiltiy 
and improved EMI 
characteristics. 


Secondary cache 
for top performance. 


Diagnostic LED‘s — useful 
for systems with no video 
controller. 


Up to 64Mb of main memory. 


All connectors accessible internally. 


Shrouded gold plated connectors. 


Highly integrated — includes standard storage and 
communications controllers. 


IBM PC-AT is a registered trademark of International Business Machine Corp. 


sensibly offered avenues of compati- 
bility from their stp Bus boards to 
competing embedded computer tech- 
nologies. 

Exemplifying this trend, Pro-Log 
(Monterey, CA) has, over the last 
year, formed a number of strategic 
relationships with makers of pro- 
grammable logic controllers (PLCs). 
These partners include such firms as 
Allen-Bradley, GE and Modicon. The 
agreements let Pro-Log build inter- 
face cards to the various PLC compa- 
nies’ architectures. In the case of 
Allen-Bradley, for example, Pro- 
Log’s stD boards can have direct ac- 
cess to Allen-Bradley’s commu- 
nications channel schemes: 
Data-Highway and Data-Highway 
Plus. In addition, Pro-Log cards can 
access remote 0 schemes such as 
Allen-Bradley’s 1771 0 subsystem. 

“We’re not going to replace PLCs in 
applications for pure 1/0,” says Paul 
Virgo, director of marketing at Pro- 
Log. “There are applications where 


COMPUTERS AND SUBSYSTEMS 


system designers want to tie their 
PLC V/O control into systems the PLC 
doesn’t support, such as disk man- 
agement or alternative networking 
choices.” 

A system may require high-reso- 
lution graphics, for example, as well 
as some kind of realtime control. A 
PLC ladder processor can do some 
level of operator interface by sending 
status over the serial link to a termi- 
nal, but there’s a time lag between 
the realtime 1/0 control action and 
when it appears on the screen. 
“Offering the ability to connect to 
their [PLc’s] 1/0 scheme and those 
PLCs is a way of making our multi- 
processing capabilities as useful as 
possible in the controls market,” 
says Virgo. “In multiprocessing 
you're not overlaying one environ- 
ment with another; you’re keeping 
the bos totally separate from the 
realtime control environment. As a 
result, there’s no risk of crashing 
your program because something 


MWA 486SX-20/25MHz © 386SX-25/33/40MHz ¢ 486DX2-50, 


memory 
internal cache 


configuration 


for 486 


¢ 2,1,1,1 Burst line fill to 486 
¢ No wait state penalty for cacheless 


¢ 0, 32 or 128KB cache for 386SX 
¢ 0, 64 or 256KB second level cache 


¢ Flash EPROM (1Mb or 2Mb) 

¢ Floppy controller with built-in 
digital data separator IDE AT 
Winchester interface (16 bit) 


HMsSystems Inc. 
2192 Dupont Dr., Suite 214, Irvine, CA 92715 
(714) 955-2043 FAX (714) 955-1849 


For More Information 
Call 1-800-800-1357 


unexpected happened in the real- 
time control in the middle of doing a 
disk access.” 


Bf Multiprocessing from Pro-Log 
Pro-Log’s Multimaster multipro- 
cessing scheme lets up to seven 286, 
386 or 486 cpus share both data and 
vo over the backplane. The com- 
pany’s most powerful board with 
Multimaster support is the 7874, a 
486-based stp Bus computer. Avail- 
able with a 25- or 33-MHz 486, the 
7874 offers full 32-bit data transfers 
to the 4 or 16 Mbytes ofon-board RAM. 
The cpu board may be used with any 
stp vo card that conforms to the STD- 
80 Series specification for adding on 
application-specific 1/o functions. 
Microsoft’s MS-DOS 5.0 operating 
system resides on a flash memory 
solid-state disk drive, permitting the 
system to operate in shock, vibration 
and temperature conditions that are 
unsuited to rotating disk drives. A 
true SBC computer, the 7874 includes 


Processor Options Available: 


386SX 25, 33 or 40MHz 
486SX 20 or 25MHz 


486DX 33 or 50MHz 
486DX2 50 or 66MHz 


General Specifications: 


¢ 2 to 16Mb memory for 386SX, 
4 to 64Mb memory for 486 using 
1Mb, 4Mb or 16Mb SIMMS 

Zero wait state paged interleave 


¢ 2 Serial ports with full handshaking 

¢ 1 Parallel port (bi-directional) 

¢ Keyboard and PS/2 Mouse port 

© 387SX socket 

* Serial , Parallel, IDE and Floppy 
can be separately disabled and/or 
relocated 

* Clock/Calendar/CMOS RAM with 
built-in Lithium battery 10 years 
life expectancy 

¢ ISA bus with buffered control signal 

¢ Port 80H diagnostic LED's 
(P.O.S.T.) on board 

¢ Power consumption: 
386SX 1.2amps approx. 
486DX33 2.0 amps approx. 


These specifications are subject to variation. 


In the U.K.: HMSystems plc, Minstrel House 


220 The Vale LONDON NW11 8HZ ® Tel: 081-209 0911, FAX 081-209 0912 
CIRCLE NO. 62 


Performance ratings are MIPS. Actual performance figures will vary depending on the hardware & 
software configuration of your system. (The above numbers reflect optimized platforms.) 


COMPUTER DESIGN DECEMBER 1992 121 


BPRODUCT FOCUS: STD BUS CPUs 


COMPUTERS AND SUBSYSTEMS 


standard AT peripheral devices, in- 
cluding keyboard interface, two RS- 
232 serial ports, a parallel port, 
interrupt controllers, counter/timer, 
DMA controllers, floppy and IDE hard- 
disk controllers, and a battery- 
backed, realtime clock. 

At last fall’s Buscon, PC/104 stan- 


a 


dard modules generated some ex- 
citement. Aspokesman for Motorola, 
for example, remarked that PC/104 
represents a potential threat to VME 
over the long term. Clearly, the 3.85 
x 3.6-in. PC/104 form factor offers 
direct competition to stp. Reflecting 
yet another example of the trend 


and debugging tools you'll need to generate 


variety of platforms like MS-DOS, SUN, HP and VAX. 


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clude ‘lifesaving’ support from Eyring's real-time experts to help you 


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cross or native code that can be shared by a 


| i 
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productivity and minimize project costs. 


anew ua 
a= Be 
a 26 7 


CIRCLE NO. 63 


122 DECEMBER 1992 COMPUTER DESIGN 


toward solutions, one STD maker, 
WinSystems (Arlington, Tx), has de- 
cided to make use of PC/104 as a 
mezzanine bus. “There will be some 
competition between PC/104 and 
stp,” remarks Bob Burckle, vice- 
president of WinSystems. 

Targeted for low-cost embedded 
system applications, the WinSys- 
tems MCM-SX386 offers both stand- 
alone operation and expansion 
options with either the stp Bus or 
PC/104 bus. The MCM-SX386 pro- 
vides a common computer core from 
which customers can add off-the- 
shelf or user-designed IEEE 961 stp 
Bus or PC/104 expansion modules. 

The two expansion methods let 
you conform to open-standard archi- 
tectures without having to pay for 
expensive proprietary solutions. At 
the heart of the board is a 33-MHz 
386SX. Up to 4 Mbytes of parity- 
checked DRAM can be installed on the 
board. An on-board EPROM socket 
supports the BIOS and extensions, 
plus a bootable Rom disk of up to 440 
kbytes. All the basic aT peripheral 
functions are included on-board. @ 


STD BUS 
Vv40 CPU CARD 


V40 CPU 8,10,16 MHZ 
BATTERY BACKED 


MEMORY/CAL.CLK 

NAT. 8573 H.S. CAL.CLK. 0 WS 
COM1,2 FULL RS-232 BUFFERS 
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FIVE 32 PIN MEM. SOCKETS 


QUANITY DISCOUNTS 
CONTACT FACTORY: 818-915-5502 


MICRO-AIDE 
CORPORATION 


685 ARROW GRAND CIRCLE 
COVINA, CA 91722 


CIRCLE NO. 87 


BNEW PRODUCT DEVELOPMENTS 


CAE/CAD DESIGN TOOLS 


pod99 90d 000 |. 
2 whe 


ate ee ee 
-peoo0o0O0O0C00 


©°0090900 
ale HO00606 
HGo0 006000 WU 
ul? 
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°° 
00690000000 =, 
J * Cree ee 


oT oO 
‘1 O @ 600060 4 
2 O16 


a, 


Press <Left> or <Space> at the line starting point. 


a 


The 32-bit architecture of the Tangopro pce provides features such as copper pour (blue 
area in upper right) and routing of curved traces. The submicron database supports 
routing of fine-pitch traces and lets you control component rotation down to 0.1°. 


—E Microsof Word - 
3 TANGOPRO.DOC 


i i s 
weg | item selected 


s personal computers and the 
A software that drives them be- 

come more powerful, pc-based 
EDA tools are closing the gap that 
separates them from their sophisti- 
cated workstation-based counter- 
parts. The latest example of this 
trend, Tangopro pcB from Accel 
Technologies, is a suite of printed 
circuit board (PcB) design tools that 
uses a 32-bit architecture running 
under Microsoft Windows 3.1 to pro- 
vide workstation-caliber features on 
the Pc. 

The Tangopro suite consists of a 
PCB layout tool, an optional high- 
speed autorouter and a library man- 
ager, which provides library inte- 
gration of schematic and PCB 
component data. The system com- 
plies with the Windows memory 
management and user interface 
standards to ensure that the tool 
looks and feels like other popular 
Windows applications. The sub- 
micron database resolution permits 
full imperial and metric support 
down to 0.0001-in. or 0.01-mm grids 


and lets you control the rotation of 


Windows-based PCB tool suite 
boasts workstation features 


components down to 0.1". 

TangoPro’s object-oriented data- 
base and its support of up to 16 
Mbytes of extended memory effec- 
tively eliminate component limits on 
your designs. The tool also provides 
dialog boxes and menus to assist you 
in implementing difficult design 
concepts such as pad stacks and 
blind/buried vias. Prompt and sta- 
tus lines give online information, 
while the graphical icon-based tool- 
bar provides access to often-used 
commands. Context-sensitive help 
gives you nearly the entire contents 
of the tutorial and reference manu- 
als online at any time. 


B Attributes defined 


The tool suite is flexible enough to 
let you define every attribute on the 
board, including grids, tracks, pads, 
polygon fills, text, and layers. Up to 
99 layers are supported, 88 of which 
may be defined by the user without 
limit to the number of copper planes. 
Polygons may be placed on signal 
layers and poured with copper in 
solid or hatched fills. Traces may 


then be plowed out of the fills. In 
addition to 45° and 90° orthogonal 
traces, curved traces may also be 
manually routed on the board for 
high-speed digital and analog de- 


| signs. 


Available as an option to Tango- 
PRO PCB is TangoPRO Route, a 32-bit 
autorouter with a rip-up and recon- 
struct algorithm letting it iterate to 
100-percent completion of complex 
pcBs. Completely integrated within 
TangoPRo Pcs, the router’s options 
are set from menus within the pcp 
tool, where they may be executed, 
paused or halted. The autorouter 
supports the full capability and ca- 
pacity of TangoPRO PcB, including 
display options, zoom and pan con- 
trol, blind and buried vias, and num- 
ber of components, nets and pads. 

TangoPRO requires a system con- 
figuration with Ms-Dos 5.0 or higher, 
Windows 3.1 or higher, a 386 or 486 
IBM PC or compatible, 8 Mbytes of 
RAM (16 Mbytes with the auto- 
router) and 10 Mbytes of hard disk 
space. A mouse is also recom- 
mended. TangoPRO PCB is priced at 
$5,950, and the autorouter at 
$10,950. Both will begin shipping in 
January of 1993. — Mike Donlin 


TangoPRO PCB 
at a glance 


e pcB layout tool suite with library 
manager and optional autorouter 
capabilities, all based on 32-bit 
architecture and Windows 3.1 


e Submicron database provides res- 
olution down to 0.0001-in. or 
0.01-mm grids and allows user- 
definable component rotation 
down to 0.1° 


e Up to 99 layers 0.1° supported, 
88 of which may be user-de- 
fined without limit to the num- 
ber of copper planes 


¢ Tangorro Route is a 32-bit auto- 
router that supports uniform and 
non-uniform grids and simulta- 
neous routing on up to 30 layers 


Accel Technologies 
6825 Flanders Dr 

San Diego, CA 92121-2986 
(619) 554-1000 


Circle 287 


COMPUTER DESIGN DECEMBER 1992 123 


BNEW PRODUCT DEVELOPMENTS 


SOFTWARE & DEVELOPMENT TOOLS 


design and simulation 


n integrated development en- 
A vironment for realtime con- 
trol systems is the result of a 
cooperative effort between The 
Math Works and dspace GmbH. The 
Math Works is supplying its 
Simulink system-simulation and 
code-generation software, which will 
be integrated with dsPACE’s digital 
signal processor (DSP) hardware and 
software. The combination of simu- 
lation software with fast psp hard- 
ware provides a platform for dy- 
namic realtime testing and analysis 
in an environment that can auto- 
matically generate code when the 
design phase is complete. 
Simulink is based on Matlab, The 
Math Works’ interactive environ- 
ment for numeric computation. 


Hardware/software combo debuts for realtime 


Matlab/Simulink 
from The Math 
Works can, running 
ona host computer, 
generate C code 
that compiles and 
runs on psp hard- 
ware from dspace. 
This lets you simu- 
late a realtime sys- 
tem on your host 
and observe its ac- 
tual behavior on 
the target board by 
feeding back data 
to the simulation 
model. 


NEC disk products also 
include the smallest 
and lightest 3.5" 
format floppy disk 
drive available. 

just .6" high and 

4" x 4" itis 

only a little 

larger than 

the media 

itself 


© 1992 NEC Techn 


124 DECEMBER 1992 COMPUTER DESIGN 


SOFTWARE & DEVELOPMENT TOOLS 


Matlab contains algorithms and 
functions for digital signal process- 
ing, control system design, neural 
networks, dynamic system simula- 
tion, and optimization, among other 
functions. Simulink offers a graphi- 
cal user interface (GUI) that lets you 
build block diagrams and hierarchi- 
cal models. Connected blocks can be 
defined as a superblock, and can 
then be combined with other blocks 
at the next higher level. 

In addition to functional blocks, 
such as integrators and filters, 
Simulink provides sources and 
sinks—blocks that can generate sig- 
nals to flow through the model and 
blocks that receive signals from the 
model for use in analysis of the sim- 
ulation. Simulink uses industry- 
standard Guis, including the 
osF/Motif flavor of X-Windows, Mac- 
intosh and Microsoft Windows. 

As originally designed, Simulink 
stops at the simulation stage. But 
now The Math Works supplies a C 


code generator that can produce ap- 
plication code for a target system 
once the design has advanced suffi- 
ciently. Using the Simulink C code 
generator, you can output C source 
code directly from Simulink block 
diagrams. When the underlying Mat- 
lab function and S-function blocks are 
contained within a block diagram 
model, you can fill in the correspond- 
ing functions with your own code. 
The C source can then be compiled 
for the target hardware environment, 
and the data compiled from running 
on the target can be fed back to the 
Simulink model to observe the be- 
havior of the real system. 


B Partnership enhances product 

The partnership with dspace 
gives Simulink users access to a 
very high-speed target environment 
based on Texas Instruments’ DsPs. 
dspACE hardware environments 
range from plug-in AT bus boards to 
full-sized systems to specialized tar- 


get processor systems such as Auto- 
box. Autobox is used for testing de- 
signs in automobiles under real- 
world conditions, such as on the test 
track. Changes made to parameters 
in the Simulink model are automat- 
ically fed to the compiled code in the 
hardware, so that the behavior of 
the system can be observed in real- 
time. 

The Math Works and dsPACE have 
collaborated to provide interfaces 
between the dspAcE hardware and 
Simulink. In addition to processor 
boards, dSPACE provides Dsp-based 
vO hardware, with specialized 1/o 
software for real-world devices such 
as optical encoders and other sen- 
sors and actuators. 

You can put together what 
amounts to a personal simulation 
system for about $30,000. Matlab 
and Simulink, along with the C code 
generator, are available from The 
Math Works for about $22,000. Ap- 

Continued on page 126 


new 1.8” HD from NEC. Just the thing for palmtops. 


Another elephant joke? No, another innovation from NEC. At only 
2" x 3” and 2.3 oz., our new 1.8” hard drive is one of the smallest 
and lightest available. And it’s also one of the largest, with a choice 
of 42MB or 85MB. At 5400 RPM there’s no com- 
promise in performance either. All on just 5 volts. 

To find out how we can improve your 


memory, call 1-508-264-8941. 


Because t is the way you want to go. 
cq» INSTANT DATA ACCESS (IDA) DIAL (617) 494-8338 DOCUMENT NO. 1055 
CIRCLE NO. 64 


COMPUTER DESIGN DECEMBER 1992 125 


ENEW PRODUCT HIGHLIGHTS 


— 


Continued from page 125 

propriate DSP-based simulation 
hardware, along with the interfaces 
to The Math Works environment, 
are available from about $8,000, de- 
pending on configuration and op- 
tions, from the us. distributors of 
dsPACE products. 


—Tom Williams 


Simulink/dSPACE 
at a glance 


¢ Supports digital signal process- 
ing, neural networks, dynamic 
simulation, etc. 


¢ cui for block and hierarchical 
block diagrams 


e Runs under osrsvotif, Macintosh 
and MS-Windows 


e Supports C code generation 
from block diagrams 


¢ Supports dspace high-speed psp 
processor and vo boards 


e Interfaces allow interactive de- 
bugging and code modification 
in realtime 


The Math Works 
24 Prime Park Way 
Natick, MA 01760 
(508) 653-1415 


Circle 288 


dSPACE GmbH 
An der Schoenen Aussicht 2 
4790 Paderborn, Germany 
011-49-0525 1-1638-0 


Circle 289 


Trademark Information 
UNIX is a registered trademark of AT&T 
Bell Laboratories. 

PAL is a registered trademark 

of Advanced Micro Devices, Inc. 
SMART-POWER is a registered 
trademark of Nartron Corp. 

CDA and BurstRAM are 

trademarks of Motorola, Inc. 

SCOPE and ASSET are trademarks of 
Texas Instruments, Inc. 

IRIS POWERVISION is a trademark 
of Silicon Graphics, Inc. 


RealTimeX is a trademark of 
Concurrent Computer Corp. 


Zone Bit Recording is a registered trade- 
mark of Seagate Technology, Inc. 


SOFTWARE & DEVELOPMENT TOOLS 


Optimizing C compiler tightly 
coupled to realtime OS 


n ANSI C compiler with both 
A global and interprocedural 

optimizations for realtime ap- 
plications is also the first C compiler 
to be produced by a realtime operat- 
ing system vendor. The Ultra C com- 
piler from Microware is tightly cou- 
pled with the company’s OS-9 and 
OS-9000 realtime operating sys- 
tems, incorporating as it does a li- 
brary of realtime system calls for 
those oss. Ultra C supports lan- 
guage and target processor indepen- 
dence with an intermediate code (I- 
Code) architecture through most of 
the compilation process. 

Currently, Ultra C supports all 
common versions of ANSI C, and will 
soon support C++, with other lan- 
guages to follow in the future. The 
compiler also supports the full Intel 
80X86 and Motorola 68XXX lines of 


processors and it will soon support | 


RISC and 64-bit processors. Between 
the compiler’s language-specific 
front end and its processor-specific 
code generator are linking and opti- 
mizing operations that are per- 
formed on the I-Code. Then there is 
a fourth assembly level “clean-up” 
stage of operation prior to final link- 
ing and object code generation. 

The I-Code optimizer and linker 
is called Ilink and it produces an 
intermediate code representation of 
a program rather than an object 


code representation. The next stage | 


is called Iopt, which is the interme- 
diate code optimizer. Since the [link 
provides an I-Code representation of 
an entire program, the optimizer 
can oversee the whole program, op- 
timizing it on several possible levels. 


It can perform local optimization | 


within straight-line code, or it can 
perform global optimization across 
straight-line code, but within a func- 
tion. Thanks to the I-Code represen- 


tation, Ilink can also reach across all | 


functions and data to optimize the 
program as a whole. 

Source files can be linked in two 
ways. They can be compiled into re- 
locatable object files and then 
linked, or I-Code files can be linked 
with other I-Code files and then op- 
timized. The former method lets you 


optimize within source files, but not | 


across them, while the latter lets | | 


you optimize across the whole pro- 
gram. The latter option also in- 
creases the compile time. A new fea- 
ture with Ultra C is that C library 
modules and operating kernel sys- 
tem call modules are supplied in 
I-Code as well as in object code. This 
gives you the option of linking these 
library modules at the I-Code level 
and performing optimization across 
not only the application code, but 
the library code as well. 

The back end of the compiler 
translates the I-Code into target- 
specific assembly language. It then 
lays out data areas, assigns regis- 
ters and generates code to access 
global data. There’s an assembly- 
level stage of optimization that 
cleans up some of the code by doing 
such things as merging sections of 
duplicated code. Then the tool per- 
forms the final step of generating 
machine language. 

Ultra C complies with ANsI X3J11 
1989 and ISO/IEC9899:1990 specifi- 
cations. Libraries include system 
calls for OS-9 and OS-9000 kernels. 
The language processor can accept a 
variety of different source programs, 
including Microware’s previous 
compilers, strict ANSI code and ANSI- 
extendible code. 

Ultra C is priced at $1,250 and is 
shipping now. —Tom Williams 


Ultra C at a glance 


¢ Language-independent front end 


 Processor-independent back end 


¢ Implements optimization in 
intermediate code (|-Code) 


© Optimization at the local, global 
and interprocedural levels 


¢ C libraries and OS-9 and 
OS-9000 system call libraries 
supplied in |-Code 


© Can link code as |-Code or as 
object code modules 


Microware 

1900 N.W. 114th St 
Des Moines, IA 50325 
(800) 475-9000 


Circle 292 


126 DECEMBER 1992 COMPUTER DESIGN 


©1992 Heurikon Corporation 


, 


Your success depends on having a firm grasp on today’s performance choices. 
Technology, however, is only the beginning. Effectively integrating those choices 
demands performance from hardware and software alike. You should have the 
flexibility to select from standard or custom configurations. 


Heurikon provides you with total solutions. Whether you use VME, Multibus or a 
proprietary platform we deliver you the real-time performance for your applica- 
tion. With Heurikon you have more than a grasp on the problem, you’ve got a 
handle on the solution! 


CIRCLE NO. 65 


With Heurikon 
Integrated VME 
Systems... 


Get 


Realtime 


HEURIKON” 


A COMPUTER PRODUCTS COMPANY 


Heurikon Corporation 
8310 Excelsior Drive 
Madison, WI 53717-1938 


800 356 9602 
Heurikon Europe 


+44 494) 88 32 32 


ENEW PRODUCT DEVELOPMENTS 


COMPUTERS & SUBSYSTEMS 


ACCESS.bus hardware released 
for industrial and commercial environments 


§ bus has been relatively slow in 
gathering momentum. The basic 
idea was to bring some order to the 


interconnection of a broad range of | 


accessory devices, such as keyboards, 

locators and bar-code readers. 
Digital Equipment Corp and a 

handful of other OEMs have been im- 


was intended to handle up to 14 
different devices on a single serial 
cable, which could be as long as 8 
meters. The early specification, 
however, left some leeway for imple- 
mentation options, and CATC’s ap- 


| proach handles up to 125 devices, 


while extending the 25 ft to 250 ft 


Computer Access Technology's Access.bus standard ar board provides for the connection 
of up to 125 peripheral devices to a single communications port in a pvat computer. An 
access.bus development support kit is also available. The controller board is co-marketed 
with Philips. 


plementing ACCEss.bus, but only re- 
cently has it started to catch on. 
Earlier this year, for example, an 
ACCESS.bus industry group was 
formed by 22 manufacturers. In ad- 
dition, a company has been founded 
to exploit the benefits of ACCESS.bus. 
Computer Access Technology Corp 
(catc—Sunnyvale, CA) has begun in- 
troducing products that let up to 125 
peripheral devices connect to a sin- 
gle communications port in a PC/AT 
system. 

ACCESS.bus is designed to handle 
relatively slow computer input from 
accessory devices such as key- 
boards, mice, bar-code readers, mag- 
netic-card readers, modems, and 
some signal transducers for real- 


with an ACCESS.bus adapter. 

The board uses the basic Signetics 
I[2|C configuration and interface, 
with an integral Signetics 8XC654 
microcontroller; it can handle data 


ntroduced over a year ago, ACCESS. | time control applications. Initially it | ware drivers. A Windows 3.1 version 


of the manager program is optional. 


B Commercial and industrial 

The primary offering of CATC is a 
standard 16-bit aT/ISA half-board (4.2 
x 6.5-in.) design that fits in a single 
slot and provides two ACCESS.bus 
connectors. An 8k x 8-bit SRAM buffer 
memory is included on the board. 
The unit controls a standard 


| ACCESS.bus network, which lets you 


add peripherals in several ways. 
catc has also recently added to its 
product line a compact PC/104 con- 
troller to handle industrial applica- 
tions. The unit has a smaller form 
factor (3.6 x 3.8-in.) but is function- 
ally the same as the AT/ISA version. 
Says catc president Dan Wilnai, 


| “The PC/104 accEss.bus module ex- 


ploits two new open standards ide- 


| ally suited to embedded control ap- 


plications. The ultra-compact, 


| stackable module architecture of the 


rates of up to 80 kbits/s (100 kbits/s | 


minus overhead). In addition, the 
ACCESS.bus cable carries a +12-V 
supply voltage for powering each de- 
vice. The cable carries up to 500 mA. 

CATC’s board is supported by an 
extensive software package, includ- 
ing on-board microcode to control 
physical AccESS.bus devices and an 
ACCESS.bus manager program that 
runs as a TSR under the PC/AT DOS 
operating system, routing control 
and applications messages between 
the physical devices and their soft- 


PC/104 standard makes it easy to 
design the full capability of a pc into 
all kinds of equipment and instru- 
mentation, while the ACCESS.bus se- 
rial bus communication standard 
based on the I|2]C physical layer 
protocol lets the designer connect 
multiple sensors or actuator devices 
to a single 1/0 port.” 

At the electrical level, AccESsS.bus 
functions as Philips initially defined 
its I[2|C setup. The host and devices 
are connected to both the data and 
clock lines in a “wired-AND” logical 
configuration. The wired-AND is im- 
plemented by connecting the data 
and clock output stages of each bus 
node to the lines through open-col- 
lector or open-drain transistors. 
These devices are included on exist- 
ing I{2]C components. The wired- 
AND configuration lets any of the bus 
nodes force either line low. When 
there’s no output from any bus node, 
the lines are held high with pull-up 
current sources in the host. All de- 
vices sense the level on both the 
clock and data lines. 

Because of its relatively straight- 
forward implementation and arbi- 
tration based on the same wired-AND 
configuration, the bus is basically 
immune to disruptions from the live 
insertion of additional peripherals. 


128 DECEMBER 1992 COMPUTER DESIGN 


COMPUTERS & SUBSYSTEMS 


While this is of some value in a 
commercial or desktop application, 
it’s very important in industrial ap- 
plications, where it could greatly 
simplify servicing, monitoring, up- 
dating, and downloading informa- 
tion. To avoid rebooting a system in 
such situations could result in sav- 
ing appreciable downtime. 

CATC offers a development support 
package that contains a controller 
board, an ACCESS.bus mouse, expan- 
sion box, cables, and an 87C751 mi- 
crocontroller. The kit also includes a 
comprehensive software package and 
user’s manual. The software package 
consists of on-board microcode and 
the Ac CESS. bus Pp neger, as well as 


and control program. Bates ce code for 
generic device driver interfaces to 
the pc and for ACCESS.bus device soft- 
ware modules is also included. 
cATC claims that the low price of 
the controller boards—$86 for the AT 
version in lots of 1,000—will go a 
long way to assure the rapid accel- 
eration of ACCESS.bus technology. 
Available now, the development sup- 
port package sells for $1,500 and the 
PC/104 modules for $245. 
— Warren Andrews 


ACCESS.bus 
at a glance 


e access.bus controller board 
e Up to 125 peripherals 


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with extender) 


¢ Connects multiple interactive vo 
devices 


e Uses low-cost I[2]C microcon- 
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© Connects keyboards, mice, 
trackballs, digitizers, scanners 


e Available as aT/isA or PC/104 


¢ Development kit available 


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CIRCLE NO. 67 
COMPUTER DESIGN DECEMBER 1992 129 


BNEW PRODUCT DEVELOPMENTS 


COMPUTERS & SUBSYSTEMS 


Intel beefs up Multibus line using 486 processors 


hile the board industry 
W speculates on Futurebus+ 

and enhancements to Multi- 
bus and vME that haven’t yet achieved 
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CIRCLE NO. 68 


130 DECEMBER 1992 COMPUTER DESIGN 


of Multibus’s fast processing capa- 
bility—take advantage of Intel’s lat- 
est family of 80486 processors. 

The product introductions com- 
prise three Multibus II single-board 
computers (SBCs) and a high-perfor- 
mance 486-based Multibus I card. 
All three sBcs are pc-compatible 
boards; the most complete is the 
Embedded Workstation. In addition, 
the company has introduced a new 
customer service capability to help 
designers and users of Multibus and 
iRMX products. 

The three new SBCs are the isBC 
486DX66, the issc 486/166SE and 
the isBc 486/150. The 486DX66 and 
486/166SE use Intel’s 66-MHz 
486DX2 processor, while the 


| 486/150 uses the 50-MHz version. 


Intel’s DX2 technology lets the mi- 
croprocessor operate at double the 
system clock speed. The 66-MHz DX2 
processor, for example, works with 
33-MHz-based systems, while the 
50-MHz version works with 25-MHz 
systems. Intel’s 66-MHz 486DX2 is 
rated at 54 Mips, while the 50-MHz 


| device operates at 41 Mips. 


“DX2 technology gives new cus- 


tomers the highest-performance 


Multibus II single-board computers 
on the market,” says Dick Binns, 
Multibus marketing manager at 
Intel. “For our existing customers, 
the new Embedded Workstation, the 
isBc 486/166SE and the isBc 486/150 
are plug-and-play upgrades to exist- 
ing products. They are so compatible 
that customers merely need to check 
their timing loops and go. No other 
changes to the system hardware or 
software are required.” 

The Embedded Workstation is the 
most highly integrated ssc of the new 
offerings. It includes high-end Pc 


| graphics, integrated Vo and standard 


pc-compatible software that uses the 
high-bandwidth multiprocessing 
power of the Multibus II architecture. 
It can carry up to 32 Mbytes of on- 
board SIMM DRAM, IDE or SCSI periph- 
eral interface and optional Super VGA 
graphics or pc Ethernet networking. 
On the software side, the Embedded 


_ Workstation supports DOS, iRMXx for 


Windows and UNIX System V Release 
4.0, Version 3. 
The top performer of Intel’s tradi- 


| tional Multibus II ssc releases is the 


166SE, a superset of the isBc 


BNEW PRODUCT DEVELOPMENTS 


COMPUTERS & SUBSYSTEMS 


Intel introduced three new Multibus II single-board computers at this fall’s Buscon East, 
becoming the first company to offer a Multibus II ssc based on DX2 microprocessor 
technology. The issc 486/150 (left) utilizes the 50-MHz Intel 486DX2, rated at 41 Mips. 
The issc 486DX66 Embedded Workstation (center) is pc-compatible and uses the 66-MHz 
Intel 486DX2 microprocessor. The issc 486/166SE (right) is a highly integrated cpu board 


that also uses the 66-MHz processor. 


486/133SE. The latest version in- 
cludes scsi and Ethernet connectors, 
can handle anywhere from 8 to 64 
Mbytes of byte-parity-protected, fast- 
page DRAM, and includes sites for 
EPROM and flash memory support. 
The Multibus I board, the isBc 
486/12SDX2, is the highest-per- 
forming Multibus I ssc from Intel— 
or from anyone, for that matter. The 
board takes advantage of the com- 
pany’s DX2 technology and features 
a 66-MHz 486 that brings the board 
up to the 54-Mips performance level. 
Despite the fact that Multibus I 
has passed its peak, continual 
board-level upgrades have kept the 
bus viable in many applications. 
“This new board,” says Binns, “dem- 
onstrates Intel’s continued commit- 
ment to the Multibus I product line. 
We have shown over the years that, 
as Intel provides new microproces- 
sor technology, we will make that 
available in our Multibus I designs. 
Because the X86/12 single-board 
computer architecture is arguably 
the most popular and prevalent in 
the total single-board computer in- 
stalled base, we pay particular at- 
tention to our existing customers.” 
Intel is not only bringing a new 
family of boards to the Multibus ta- 
ble, but it’s also adding a new service 
organization to its existing sales op- 
eration. The new organization for 
Multibus I, Multibus II, irmx, and 
iRMX for Windows products provides 
a direct line for customers in need of 
technical or business information. 


All four isBc boards are available 


now. For quantity one, the 486DX66 | 


is priced at $5,250 (no memory), the 
486/166SE at $7,515 (8 Mbytes 


memory), the 486/150 at $5,737 (8 
Mbytes memory), and the 486/ 
12SDX2 at $7,120 (8 Mbytes 
memory) and OEM pricing applies. 
— Warren Andrews 


Multibus SBCs at a glance 


© 66-MHz 80486 processor-based 


e Uses Intel's DX2 clock-doubling 
technology 


¢ High-end pc graphics 


¢ Integrated vo plus IDE and scsi pe- 
ripheral interfaces 


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CIRCLE NO. 69 


COMPUTER DESIGN DECEMBER 1992 131 


“Design for X:" 
A new push for 


manufacturability, 
testability and 


reliability 


learned a little about reliability analysis work- 

ing for the Department of Defense 25 years ago. 

Let’s say you’re working on a massively destruc- 

tive weapons system. You can’t fully test the 

thing. You hope and pray, in fact, that it will 
never be used. But you must be absolutely certain— 
certainty, according to the Department of Defense is 
99.968 percent—it’ll work if you need it. 

Reliability is but one of the product-support varia- 
bles CAE tool vendors are considering under the ban- 
ner of “Design for X.” Joseph Costello, president of 
Cadence Design Systems (San Jose, CA) and co-chair- 
man of EDAC, the CAE tool manufacturers’ trade asso- 
ciation, called attention to this during a press 
luncheon at the Design Automation Conference in 
July. The “X” stands for all the back-end processes 
designers and design tool vendors are just starting to 
consider—assembly, manufacturing, reliability, re- 
pairability, serviceability, and test. 


Bf Focusing on the nuts-and-bolts 


Most of the attention of CAE software developers (and 
of trade magazine editors) has been concentrated on 
the glamorous, performance-driven design side of the 
engineering world. Less attention has been placed on 
bread-and-butter issues, such as the cost of manufac- 
turing the supersystem and the need to shave pen- 
nies—if not dollars—from the total. We can design 
great electronic systems, but can we test them? Can 
we manufacture them cheaply and in volume? Can 
we service them when they break? Do we know how 
long they’ll last? Attention to the stringent, less glam- 
orous requirements of Design for Xis where we'll need 
to look for answers to such questions. 

Racal-Redac (Mahwah, NJ and Tewksbury, U.K.) was 
among the first companies to emphasize design for 
manufacturability as an approach to PcB layout. Men- 
tor Graphics (Wilsonville, OR) is amore recent convert; 
its Manufacturing Advisor was introduced late last 
year. Cadence, with solid strength and experience in 
ASIC design, is just beginning to enhance its system- 


132 DECEMBER 1992 COMPUTER DESIGN 


MIXED-SIGNAL DESIGN Stephan Ohr 


and board-level tool offerings with improved links to 
manufacturing. 

Design for manufacturability acknowledges the 
gulf between those electrical engineers who design 
electronic circuits and those who must implement 
them on a pcp. If the truth be known, this clash of 
cultures isn’t as great between ASIC designers and 
manufacturers as it is between system designers and 
manufacturers. The Asic designers use design rules, 
cell libraries—an entire toolset, in fact—that’s been 
tweaked for the fabrication of semiconductors. On 
most frameworks you can’t invoke a simulator (analog 
or digital) without specifying which fabrication pro- 
cess youre using. Even where the Ic is designed 
entirely at a customer’s plant, it’s done with the asic 
vendor’s tools, model libraries, layout contingencies— 
in other words, with an intimate knowledge of what 
the Ic manufacturer is capable of producing. 


I The laws of physics apply 


The gap between design and manufacturing, however, 
is much wider for board-level products. There are 
differences between how designers want their board- 
level system to perform, and what you can practically 
stuffand solder onto a piece of copper-coated phenolic. 
Manufacturing and assembly engineers worry not 
just about the thickness or thinness of your traces and 
the orientation of pads and footprints, but also about 
the accuracy of hole-drilling equipment, component 
inserters and pick-and-place machinery. They think 
about how often this equipment will bend a compo- 
nent lead that fails to meet a throughhole, the rela- 
tionship between solder defect rates and lead-frame 
spacing and the percentages attached to manufactur- 
ing-induced shorts and opens. 

While the people who design high-performance dig- 
ital systems typically worry about the number of 
nanoseconds between the rising edge of a clock pulse 
and the appearance of valid data on an output line, 
the people who actually build these systems worry 
about the number of minutes the board sits in a 


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CIRCLE NO. 70 


MIXED-SIGNAL DESIGN 


chemical etching bath. Small details, easy to overlook, 
can make an enormous difference to the manufactur- 
ing engineer. Teardrop-shaped pads, for example, 
prevent the copper etchants from creating an electri- 
cal open by eating away at the sharp corners at 
junctions of pads and traces. 

The goal of design for manufacturability is to bring 
these cultures closer together: To provide a layout tool 
to the manufacturing engineer that somehow commu- 
nicates the intent of the design engineer, or a design 
tool that incorporates the capabilities and contingen- 
cies imposed by the manufacturing expert. 


Bl Closing the gap 


“The Great Wall between engineering and layout, 
between layout and manufacturing, is inevitable,” 
says John Seaton, advanced products marketing 
manager at Mentor Graphics. The company has po- 
sitioned itself among the strongest advocates of con- 
current engineering, a product development philoso- 
phy that closes the gap between design and 
manufacturing. “More than 70 percent of the manu- 
facturing cost impact,” continues Seaton, “will come 
from component choices and decisions made in the 
design environment.” 

But Seaton has no illusions that digital system 
designers will suddenly become expert in layout and 
manufacturing. “You don’t want them to worry about 
that,” he says. The better solution is to rely on a tool 
such as Mentor’s Manufacturing Advisor/Pcps, an ad- 
dition to the company’s BoardStation product that 
will provide direct, online feedback on the manufac- 
turing impact of particular board design choices. 

Racal-Redac, I believe, was among the first compa- 
nies to offer PpcB layout tools truly intended for man- 
ufacturing. Its design rule checks incorporate long 
lists of manufacturing contingencies. If you lay down 
the footprint for an so-packaged device, for example, 
the system verifies not only whether the pad sizes and 
lead pitch are correct for the device you're placing, 
but also whether the pads are oriented properly for 
the soldering technique you’re using, whether the 
placement of throughholes matches the resolution of 
your hole-drilling equipment, and even whether 
you've left enough space on a tightly packed board for 
the fingers of your component inserters and other 
pick-and-place machinery. Racal-Redac’s post-proces- 
sors provide not just the standard Gerber photoplots, 
but also numerical control (Nc) tapes for drilling and 
milling machinery. 

Key to the utility of Racal-Redac’s Visula toolset is 
a manufacturing database that lets you assign infor- 
mation to each pin or connection point. Based on the 
Informix relational database, Visula supports up to 
256 layers of information for each point, according to 
Dave DeMaria, Racal-Redac’s director of product de- 
velopment in Tewksbury. Electrical information, vol- 
tages and currents, materials, pad dimensions, 
machine tool access points, photo mask tolerances, 
preferred vendors, cost data, Nc file formats—all 
types of practical information can be accessed with a 
query from any point on the PcB layout. It’s this type 


of database, says DeMaria, that’s made Visula a 
preferred layout tool for complex new board designs 
with computer systems from companies such as Apple 
Computer and Data General. 

While implementing rules-driven design, Ca- 
dence’s Allegro board layout tools have traditionally 
been tilted toward the design part of the engineering 
process. You use them to complete a layout to get a 
better look at the layout-dependent parasitics. But 
Cadence has tipped toward the manufacturing part 
of the process with several recent announcements. 
Most prominent is a licensing arrangement with AT&T 
Bell Labs (Holmdel, Ns). Two AT&T software modules, 
design for assembly (DFA) and design for manufacture 
(DFM), will be integrated with the Allegro board design 
set and used for post-layout rule checking. The mod- 
ules, developed for telephone equipment manufactur- 
ing, will be used to verify the tolerance of solder 
masks, the shape and density of solder paste applica- 
tions, the orientation of components for soldering and 
assembly, and a long list of other tasks. 

The DFA and DFM modules are an implementation 
of a correct-by-design philosophy that Cadence is 
building in the systems arena. Typical board design 
is characterized by a number of design/analyze/fix-it 
iterations, according to Debra Ives, Cadence’s Allegro 
product marketing manager in Chelmsford. “If the 
system constraints are properly specified to the tool- 
set,” she says, “the layout tools will always make these 
visible to the user.” Manufacturability analysis, in 
fact, becomes just one of many checks the tools will 
perform to assess the viability of a design. Cadence’s 
board-level reliability assessment tool, Viable, intro- 
duced in December of 1990, for example, will assess 
the reliability of a system-level product, using ther- 
mal stresses and cost data in its calculations. 


Ef Reliability modeling technology 


For the semiconductor industry, the ability to model 
reliability would mean quicker time-to-market. The 
normal process of burn-in and reliability testing can 
delay the introduction of a new product until many 
months after the piece has been designed and a test 
program developed for it. Reliability modeling lets a 
manufacturer put together statistically significant 
data about a product even before it goes into full 
production. 

The implications of this aren’t just for weapons and 
semiconductors. An engineer at Ford Motor Company 
told me he was doing extensive work on modeling the 
in-rush current of headlamps. If you think about it, 
the filament of an electric lamp will burn itself out 
just at the point you flip on the switch. The goal of 
reliability analysis, like many other projects under 
the Design for X banner, is a less expensive product 
with a longer product life. “You want to start this on 
a cold day in Minnesota or on a hot day in Texas,” says 
Ford modeling engineer Gary Zack, “and know that 
it’s going to work.” 


Stephan Ohr is president of Indian Forest Research and 
publisher of the monthly newsletter, Mixed Signals. 


134 DECEMBER 1992 COMPUTER DESIGN 


Announcing Two New Conferences 


PUY, 


MAKING IT WORK FOR YOU 


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| eet gd early attempts at 
improving quality didn’t always prove 
successful. First there were quality circles 
and quality councils. Then came 
concurrent engineering, cross-functional 
workteams, worker empowerment and, 
now, total quality management (or TQM). 
For many companies, the attempts to 
improve quality failed — sometimes 
miserably — and all of these high- 
sounding terms — and the ideals they 
represented — become nothing but 
buzzwords. 

Perhaps more than anything else, 
companies failed at improving the quality 
of their products or services because 
there was no consistent, generally 
accepted framework within which they 
could develop their quality programs. 
Even more, there was no generally 
accepted performance standard by which 
they could measure the effectiveness of 
their quality management systems. In 
short, companies didn't know what to do, 
and didn't know what to do about it. 


The International Organization for 
Standardization (ISO) and ISO 9000 
are changing all that! 


Developed over a period of several 
years by representatives from the 91 
countries that are members of the ISO, 
ISO 9000 has become an internationally 
recognized family of specifications for 
quality assurance management systems. 

The ISO 9000 standard (really a set 
of five standards, numbered 9000 
through 9004) isn't a set of product 
specifications and it's not specific to any 
one industry. Rather, ISO 9000 defines a 
process — one that ultimately leads to 
certification — to ensure that a 
company's procedures for quality 
management and quality assurance for 
procurement, material management, 
design control, production process 
control, customer interface, and servicing 
are under control and are producing 
consistent results. It also defines 
guidelines for the activities needed in 


GLOBAL IMPACT 
OF ISO 9000 


© Worldwide political and 
trade policy trend toward 
quality registration 

¢ More than 50 nations have 
adopted the standards 

¢ 350 companies in the U.S. 
are now registered 

¢ 550,000 U.S. companies 
within the next 5 years 

e Within 5 years, quality system 

registration will be 

fundamental to doing business 

on a global basis 


each of these areas to identify, analyze 
and correct problems. 

Some of the benefits of adhering to 
the applicable ISO 9000 standard are 
obvious. First, quality and productivity 
are improved. Second, consistency in 
following other established standards is 
ensured. Third, costs are reduced by 
doing things right the first time and 
every time. The bottom-line result is that 
your company's ability to compete in the 
world market is improved. In fact, it may 
soon be impossible to compete globally 


without ISO certification. 

There's an irreversible trend in 
political and trade policy toward quality 
system registration and more than 50 
countries have already adopted ISO 9000 
as a national standard. In the U.K. alone, 
more than 20,000 companies are now ISO 
certified, and certification will soon be a 


A AM TY I LE OA NES RRL EY 
“ISO 9000 is documented 
common sense. 

There is no black magic, no 
voodoo, no great complicated 
indoctrination program. 

Just plain, old-fashioned 
common sense - 

Doing Right Things, Right!” 


Jim Carras, 
The Carman Group 


requirement for access to the European 
Economic Community (ECC). While only 
a few hundred companies in the U.S. are 
currently certified, and only a handful of 
these are electronics or computer 


ISO 9000 — DEFINED FUNCTIONS AND ACTIVITIES 


FUNCTIONS 


Procurement 


Material Management 


Production Process | 
Control F 


Customer Interface 


Design Control 


ACTIVITIES 


Statistical Techniques 


Corrective Action | 


Validation, Calibration | 
& Maintenance 


Inspection & Test | 


YOY 


Making It Work For You 


companies, it's estimated that more than 
a half-million will be certified in the next 
five years. 


Make no mistake about it, By the 
end of the decade, and most likely 
before, ISO 9000 certification will 
be a requirement for doing business 
on a global basis. 


As you might expect, obtaining ISO 
9000 certification isn't a cake walk. The 
procedures are rigorous and the auditing 


Grayhill Inc. which manufactures 
switches, solid-state relays and 
distributed control components, has 
just been registered to ISO 9001. 
Because of the registration, 
Hewlett-Packard, which audits 
Grayhill annually using its own 
three-person team, has said its 
audit would be unnecessary. 
According to Brian May, marketing 
manager for Grayhill, his company 
sought registration for several 
reasons. One was to gain an edge 
over competitors who weren't 
registered. 

“Then there's the issue of 
making Grayhill a better company 
and being able to reduce 
redundancies in our system and 
reduce our scrap rate. And then 
there's the financial payback from 
doing all of this,” says May. 


teams sent in by the organizations 
authorized to qualify a company for 
certification are thorough and soul- 
searching. Contacting the ISO for its list 
of accredited certification organizations, 
signing a contract with one of them, 
signing a check, and then exposing 


yourself to scrutiny isn't the best way to 
go about certification. 

A better way is to get educated about 
ISO 9000 first. Start by learning the 
details of the 20 specific ISO 9000 quality 
management system requirements, and 
the most important aspects of each of 
these requirements. Learn what it takes 
to define a quality management system, 
how to prepare a Quality Manual and how 
to select, train and qualify your own in- 
house auditors. Then get organized for 
implementation and implement an ISO 
9000 Quality Manual. Then contact an 
accredited certification organization. 

But how do you get educated about 
ISO 9000 and what it takes to get 
certification? Fortunately, there are 
consulting and training organizations, 
such as The Carman Group in 
Richardson, TX, that can help you 
through these early stages. They play an 
important role in the overall 
certification process, because the ISO 
expressly forbids organizations that 
perform ISO 9000 assessments and 
audits from advising companies on how 
to set up their quality systems or to 
write their quality documents. 
Companies seeking ISO 9000 
certification that don't pursue pre-audit 
or preparation services suffer a 70 
percent failure rate the first time 
through their audit. That's an expensive 
way to learn what ISO is all about. 

Before long, trying to survive in a 
marketplace that demands quality as 
much as high performance products — 
and want some proof that you can 
provide the quality you claim — will be 
impossible. ISO 9000 certification is a 
critical part of that proof and the time to 
take the first step toward certification is 
now. That first step is learning what it 
takes to become certified and The 
Carman Group can help with it's ISO 
9000 seminars created specifically for 
high technology companies, and in 
particular, for those companies in the 
electronics, computer and electro optic 
industries. 


THE ISO 9000 
STANDARDS: 


ISO 9000: Quality 
Management and Quality 
Assurance Standards — 
Guidelines for Selection 

and Use 

ISO 9001: Quality Systems 
— Model for Quality 
Assurance in Design and 
Development, Production, 
Installation, and Servicing 
ISO 9002: Quality Systems 
— Model for Quality 
Assurance in Production and 
Installation 

ISO 9003: Quality Systems 
— Model for Quality 
Assurance in Final Inspection 
and Test 

ISO 9004: Quality 
Management and Quality 
Systems, Elements and 
Guidelines 


YOU'RE IN A SELECT 
GROUP IF YOU'RE 
ISO 9000 CERTIFIED 


¢ AT&T 

¢ Bell Northern Research 
¢ Compaq Computer 

e Data General 

¢ Digital Equipment Corp. 
¢ Dupont 

¢ GE Fanuc 

© Grayhill 

¢ Hewlett-Packard 

e Lasertron 

¢ Northern Telecom 

e Prime Computer 

e Signetics 

e Square D 

e Sun Microsystems 

e Texas Instruments 

e Unisys 

e Xerox 


YYOD 


Making It Work For You 


he Carman Group Company, in association with PennWell 
Publishing, has created a specially tailored version of its 
successful three-day ISO 9000 seminars that's intended to 
meet the needs of corporate management (Presidents, 
General Managers, Sales Managers, Quality Managers, etc.) 


DAY 1: 


Recommended for corporate managers who need to 
learn about ISO 9000 and its impact on their 
organizations. 


e Benefits of ISO certification 

e Six functions covered and the activities within each 
function 

e The steps to certification and maintenance 

e Typical timeframes and fees 

e Application of ISO standards to your company 
requirements 

e The Corporate Needs Assessment 

e Strategic and operating plans 

¢ Comparison of ISO to Malcolm Baldrige Award 
and MIL-Q-9858A 


and design, test and manufacturing management (Directors 
of Engineering, VPs of Engineering, Product Managers, Test 
Engineering Managers, Senior Design and Test Engineers, 
Manufacturing Managers and Engineers, etc. ) at 
computer/electronic/electro optic OEMs and OEM suppliers. 


DAYS 2 &3: 


Recommended for those technical managers and 
engineering personnel who will actually be writing the 
documentation and procedures for ISO certification. 


e Definition of a Quality Management System 

¢ Global objectives of procedures 

¢ Relationship of each ISO 9001 paragraph to key points, 
manuals and procedures 

e¢ Write a procedure to select, train, qualify, and 
certify your own in-house auditors 

e Plan an audit/compliance schedule 

e Provides a workshop environment to gain insight from 
other company representatives 


REGISTER TODAY! 


A SPECIAL CONFERENCE SERIES PRESENTED BY PENNWELLS ADVANCED TECHNOLOGY GROUP 
Computer Design + Laser Focus World + Industrial Laser Review * Solid State Technology * Lightwave + Military & Aerospace Electronics 
SANTA CLARA, CA + BILTMORE HOTEL - MARCH 29, 30, 31,1993 
BOSTON, MA - MARRIOTT LONG WHARF - APRIL 12,13,14, 1993 


MAIL application with your check payable to: 
Seminar Coordinator-The Carman Group, Inc. 
P.O. Box 835088, Richardson, TX 75083-5088 


Seminar Location: 


or REGISTER by PHONE: 800-942-6880 
or FAX this application to: 214-669-9478 


Seminar Date: 


Company Name: 


Address: City State Zip 

Business Phone: ( ) Extension Fax: ( ) 

Name of Attendee 

i\p |_| Day 1 $295 |_| Days 2&3 $795 | | Days 1,2&3 $995 

2 |__| Day 1 $295 |__| Days 2&3 $795 | | Days 1,2&3 $995 

3; |_| Day 1 $295 |__| Days 2&3 $795 | | Days 1,2&3 $995 
Ota eh Total $ Total $ 


IF YOU REQUIRE ADDITIONAL INFORMATION, 
CALL (214) 669-9464 


Grand Total $ 


(Deduct 10% if registering three or more from the same company) 


If seminar is cancelled for any reason, the liability of the Carman Group is limited to a refund of the course fee paid. Apply a 10% discount if registering three 
or more from the same organization. Registration is not guaranteed until check or Purchase Order has been received by the Carman Group. Full refund for 
cancellations up to 2 weeks prior to the beginning of the seminar. Cancellations between 2 weeks and 3 working days prior to the start of the course are 
subject to a $150 cancellation charge. Cancellations less than 3 days prior to the start of the course are subject to the full course fee. 


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The Ultimate 


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Half size ECL Clock Oscillator 


= 


as 
160 mHZ 


Connor-Winfield Corp. introduces its new 8-pin 
DIP ECL clock oscillators. The E500 Series is available 
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These models are available with supply voltage of 
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1865 Selmarten Road, Aurora, IL 60505 
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CIRCLE NO. 173 


«gw Little PLO™ 579, 


Our new Little PLC™ measures only 4.33 x 2.85 inches 
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CIRCLE NO. 174 


COMPUTER DESIGN DECEMBER 1992 139 


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357 MHz 14-Pin 
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Connor-Winfield Corp 
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CIRCLE NO. 182 CIRCLE NO. 183 


140 DECEMBER 1992 COMPUTER DESIGN 


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COMPUTER DESIGN DECEMBER 1992 


141 


COMPUTER 7 


DESIGN and Design 


1 993 EDITORIAL CALENDAR 


Directions 
A PennWell Publication 


ISSUE SPECIAL REPORT 


TECHNOLOGY FOCUS PRODUCT FOCUS 


DESIGN STRATEGIES 


OEM INTEGRATION 


JANUARY Verilog and VHDL *DSP development tools C cross compilers Networking 
Disk drive controllers 
and associated ICs 
FEBRUARY * Bridging the buses Software tool integration Flash EEPROMs Process control 
Buscon West, ICs for desktop video 
EDAC/Euro ASIC 
MARCH Memory architectures «Multithreaded SCSI host adapter boards Data acquisition 
RISC '93, operating systems 
PCB Design ¢PC-Based CAE/CAD Tools 
APRIL* EMBEDDED COMPUTER CONFERENCE (ECC) SHOWGUIDE** 
Embedded PC/AT architectures in *Developments in 3-V ICs Device programmers Peripherals 
Computer embedded applications «Evaluating simulation 
Conference strategies 
MAY SPECIAL REPORT ON FUTURE COMPUTING: Virtual Reality 
cicc New applications for DSP Benchmarking Video D-A converters Portable computers 
programmable devices 
¢Bus standards 
JUNE* High-level synthesis and = * Small form factor VME Ultra-fast SRAMs Graphics 
DAC architectural design «Data compression 
standards and ICs 
JULY Advances in IC packaging Interfaces for DSP Real-time kernels and Imaging 
Fuzzy Logic ’93 ¢ Fuzzy/neural update operating systems 
AUGUST* Trade-offs in *RISC in real time Emulators Robotics 
programmable devices «Integrating CAE 
architectures and CAD databases 
SEPTEMBER Software testing *Futurebus+ Low-power DRAMS Instrumentation 
EuroDAC, and quality «Integrating testability into 
Buscon East, the ASIC design process 
Embedded Systems, 
Wescon 
OCTOBER* ANALOG & MIXED-SIGNAL DESIGN CONFERENCE SHOWGUIDE** 
Analog & Designing mixed *Hardware/software trade— Logic analyzers Simulation 
Mixed-Signal digital/RF systems offs in multiprocessing 
Design «Network interfaces 
Conference and interface ICs 
NOVEMBER SPECIAL REPORT ON FUTURE COMPUTING: The merging of computers and communications 
Comdex Designing for testability «PLD design tools High-resolution A-D Communications 
and manufacturability *Mezzanine buses converters 
DECEMBER* Designing the next ¢Full-system simulation VME CPU Boards Supercomputers 


generation of 
portable computers 


“Starch Readership Research Issue 


*FAX/modem ICs 


**Contact Computer Design for circulation, rates and closing dates 


PENNWELL PUBLISHING COMPANY ¢ ONE TECHNOLOGY PARK DRIVE ¢ WESTFORD, MA 01886 ¢ 508-692-0700 * Fax 508-692-7780 


ACCOUNTS REPRESENTATIVES: * WESTFORD, MA, Sue Nawoichik, Sales Manager, 508-392-2118 800-223-4259 ¢ David Singer, 508-392-2109 


¢ Secondary & mezzanine 
buses 
*Backplanes & enclosures 


«Input devices 


Printers & output devices 


* Networking interfaces, 
standards & components 


¢ Display devices & 
monitors 


« Power sources 
¢ Interconnects 


«Mass storage (disk, tape, 
CD-ROM, memory cards) 


COMPUTER 7" 


For more information, contact any of us: PUBLISHER: David L. Allen, 508-392-2111 « ASSOCIATE PUBLISHER Tim L. Tobeck, 508-392-2116 « P 
NATIONAL ACCOUNTS MANAGERS: ¢ WESTFORD, MA, Tim Pritchard, 508-392-2217 ¢ SPRING, TX, Eric Jeter, 713-353-0309 Fax 713-288-8350 and Design 
¢ CAMPBELL, CA, Diane Palermo, 408-371-7551 Fax 408-371-6239 ¢ GLEN ELLYN, IL, David Ginter, 708-469-2388 Fax 708-469-2292e STRATEGIC D rer in i 5 
800-223-4259 ¢ INTERNATIONAL SALES OFFICES: ¢ SURREY, ENGLAND, David Round, 81-770-1100 Fax 81-770-9779 « PARIS, FRANCE, 

Daniel R.Bernard, 1-39-14-6780 Fax 01-39-14-7014 ¢ MUNICH, GERMANY, Johann Bylek, 089-903-8806 Fax 89-904-3526 * MILAN, ITALY, 


Luigi Rancati, 2-70-30-0088 Fax 2-70-30-0074 « TOKYO, JAPAN, Toshio Equsa, 81-33-536-5404 Fax 03-536-5490 * ASIA, AUSTRALIA, 
NEW ZEALAND, Tom Gorman, 852-833-2181 Fax 834-5620 


A PennWell Publication 


CIRCLE NO. 78 


ADVERTISERS INDEX 


Computer Design’s 
INSTANT DATA ACCESS 
ADVERTISERS 


To receive data sheets instantly from these advertis- 
ers via FAX, dial (617) 494-8338 and when 
prompted, enter the 4 digit document number 


shown here. 


ADVERTISER 


Macrolink 
NEC Technologies 


ADVERTISER PAGE 
NO. NO NO, 


A 
Advanced Micro 


Ariel Corporation 
ATMEL Ae i 


BaAGOMIM asscssvsvereccuvsessacess 24 18 
Brooktree Corporation ree 

Brooktree Corporation 
BUSCON '93 West......... 


Cc 

Chrislin Industries........... 
GIBMCOF AG cccarestce marvete 
Compass Design 
Automation... 
Compcontrol, Inc. . 
Computer Design... 
Computer Design... 
t Computer Design... 
* Computer Design...... t. 
Connor-Winfield Corp.... 
Connor-Winfield Corp... 
CSP caciucitediepaceschvaeanavaoceees 
Cypress Semiconductor . 


D 
Diversified Technology.42- Pe bp caanaicoravas 27 
BYRSteny,. Gis. sascancestsacnagl dl anceecre scares Areca 1032 
E 
Electronic Solutions ............ Neaveehrvacsures 2 


ELMA Electronics... 
ELMA Electronics 
Embedded Computer 


Conference ........5. 2a haeegties .60 
Eyring Corporation .........122..ccc .63 
F 
Force Computers......... VGedPiensriiceaces 10 
G 
Grammar Engine............ 140... . 180 
Greenspring Computers .107...............55 
Greenspring Computers .109..... 57 
Greenspring Computers .111..... 59 
H 
Heurikon Corporation ....127.. 65 
Heurikon Corporation ....129. 67 
Heurikon Corporation ....131.... 69 
* Hitachi America, Ltd.........19.. cee 13 
HM Systems........ PTROAN 2 vcccsssasiinss SOZ 
Huntsville Microsystems......4... 4 
! 
magine That....... 139 169 
ntegrated Device 
TRCANOIOGY acincievanvgsis Massy vd 
ntegrated Systems, Inc. ...47 33 
t Intel Corporation... i 5c ee 
nvitational Computer 
Conference.......:.0 1102... 58 
POMNGS UMC yy casnecacpsacsstcteec Mover sass 30 
SO 9000....... 135-138. 71 
K 
KAD AK a cacauntiachaarad ovata 11 
L 
Lattice Semiconductor......51 29 
Logical Devices, Inc TER sss 186 


ADVERTISER PAGE CIRCLE **IDA 
NO NO. NO. 
M 
Macrolink, Inc. ......... ce MUG caccasubes cont 54... 1037 
Matrix Corporation............ 74... 47 
Maxim Integrated 
PROGUCES!.scdescss05- seer is f= fe sana 
Mercury Computer 
Systems .......... Fanass 
Micro Alliance.......... 
Micro-Aide, INC... 
MictO-SYS..o sais cccitee i 
Micron Semiconductor ......41..........+.26 
Microtec Research, Inc.......67..... mts 
Microware Sysetms Inc......35...0......24 
Mitsubishi ElectronicsDG .54............... 35 
MIZAReicuaticsiesn pers Fa 68 
Motorola Semicond 
PIS says seas seatonss 2OR2 1 sinccavaivssxex VO 
Motorola TSD Group.........57.....0. aoe 
N 
NEC Electronics .. ke ae 
NEC Technologies .. 124-125. si OAs 1055 
Needham’s Electronics... 140.... ihe 
Nohau Corporation .........139............. 167 
oO 
CaS YS MINCE areits fetetcconsexchtZs BS. oa: 


OrCAD Systems.. 
OrCAD Systems 


Pentek sess sale iuaivenrs 
Phase Three Logic . = 
PROS IGtensrcnca sto’ 


Q 
Quantum Software 
Systems; Haomtcsua/ SO oO 


R 
RadiSys Corporation ....... CV3..0.0ce 82 
Radstone Technology 
Cor| el ieee 
RISC ‘93 Overview ....... iss 
Robotrol Corporation ..... 
5 18, Fo Fal a chee ore 


‘3 
Sheldahl ............000. spe AAO raasssecees 177 
Sky Computers, Inc. ........ AGAR sere 53 
Spectrum Signal 


ProcesSiNg..........::0+++: 
Synergy Microsystems, 
Synergy Microsystems, 


1 
adpole Technology .......... 59.0... 39 
Technical Solutions.......... 2: rr 178 
Teknor ie adi INGS Bo iececarercuss 50 
TOR ERCINS NG cate veg pcev 07 see enemas 5 
t Texas Instruments........ 81 eee 
t Texas Instruments.. Baixwaieere 
* Texas Instruments.. BE © Pe ane - 
* Texas Instruments..............81 Whine 
oronto MicroElectronics ... 18 ; 12 
U 
Ultraview......... Sere Oo .. 170 
Vv 
VenturCom , es) we. 
VMetro, Inc....... sABcserasasisiasep ht 
Vail Silicon Tools, Inc....... 139 168 
Ww 
Wind River Systems ers are 43 
Z 
Z-World Engineering........ 139 174 
Ziatech Corporation.........114 Ron 
Zwick Systems, Inc. ......... 140... 183 


* Domestic only 
t International only 

** These advertisers have made arrangements to 
provide you with instant product data via Com- 
puter Design's Instant Data Access (IDA) System. 


The Advertisers Index is published as a service. 
The publisher does not assume liability for 
errors or omissions. 


SS aE, 
When your product 
advertising demands 
that you reach the 
key decision makers 
in the microprocessor 
based electronics 
OEM, 

COMPUTER DESIGN 
delivers! 


Only COMPUTER DESIGN: 


eserves today's $570 
billion microprocessor 
based electronics OEM 


*provides design 
directions, options and 
choices-with exclusive 
"“why-to" editorial 


edelivers over 100,000 
engineering managers 
and engineers-100% 
design and development 
qualified! 


ereaches over 71,000 
design and development 
engineering managers- 
more than any other 
design publication in 
the market 


eis the fastest growing 
publication in the field 


For more information on how 
to subscribe or advertise, 
please contact: Tim Tobeck, 
National Sales Manager/ 
Associate Publisher at 
(508)392-2116. 


COMPUTER ‘ech 


and Design 
Directions 


OneTechnology Park Drive 
Westford, MA 01886 
(508) 692-0700 
CIRCLE NO. 80 


COMPUTER DESIGN DECEMBER 1992 143 


COMPUTER Technology 


and Design 
Directions 


Executive Office: One Technology Park Dr, PO Box 990, Westford, MA 01886 
(508) 692-0700 Fax: (508) 692-7780 Telex: 883436 
Publisher: David L. Allen (508) 392-2111 
Associate Publisher/Editor-in-Chief: John C. Miklosz (508) 392-2114 
Associate Publisher/National Sales Manager: Tim L. Tobeck (508) 392-2116 
Administrative Assistant: Peg Alexander (508) 392-2112 
Marketing Communications Manager: Betsy Anderson (508) 392-2209 
Ad Traffic Manager: Kelly Rice (508) 392-2198 
Recruitment Advertising, Postcards/System Showcase: Sue Shorrock (508) 392-2185 
Circulation Director: Paul Westervelt (918) 832-9287 
List Rental: Bob Dromgoole (918) 832-9213 
Reprints: June Bozarth (918) 835-3161 


40 MB/SEC | 


LOW-COST VMEbus BYTE 
PARITY MEMORY with 4, 8, or 
16MB in one 6U VMEbus slot 


@ LIFETIME WARRANTY 
OTHER QUALITY VMEbus 
MEMORIES AVAILABLE ARE: 


THE Cl-VMEmory 


THE CI-VSB EDC 


Associate Publisher 
Tim L. Tobeck 


National Accounts 
Managers 


Eastern Region 

Tim Pritchard 

One Technology Park Dr 
PO Box 990 

Westford, MA 01886 
Tel: (508) 392-2217 

Fax: (508) 692-7780 
Telex: 883436 


Southwestern/ 
Northwestern Region 
Eric Jeter 

19627 I-45 N, Suite 110 
Spring, TX 77388-6030 
Tel: (713) 353-0309 

Fax: (713) 288-8350 


Northern California 
Diane Palermo 

910 Campisi Way 
Suite 1B 

Campbell, CA 95008 
Tel: (408) 371-7551 
Fax: (408) 371-6329 


Midwestern Region 
David Ginter 

800 Roosevelt Rd 
Suite E-120 

Glen Ellyn, IL 60137 
Tel: (708) 469-2388 
Fax: (708) 469-2292 


SALES OFFICES 


Strategic Accounts 
Representatives 


Eastern U.S. 

Sue Nawoichik, Sales Manager 
One Technology Park Dr 

PO Box 990 

Westford, MA 01886 

Tel: (508) 392-2118 

Fax: (508) 692-7780 


Western U.S. 

David Singer 

One Technology Park Dr 
PO Box 990 

Westford, MA 01886 
Tel: (508) 392-2109 

Fax: (508) 692-7780 


U.K./Scandinavia 
David Round 
Westmead House 
123 Westmead Road 
Sutton 

Surrey SM1 4JH 

Tel: (081) 770-1100 
Fax: (081) 770-9779 


France/Belgium/ 

Southern Switzerland/ 
Spain/Netherlands 

Daniel R. Bernard 

10, rue Michelet - B.P. 279 
78502 Sartrouville Cedex, France 
Tel: 01-39-14-67-80 

Fax: 01-39-14-70-14 


Germany/Austria/Northern 
Switzerland/Eastern Europe 
Johann Bylek 

Verlagsbuero Johann Bylek 
Stockaeckerring 63 

D-8011 Kirchheim/Muenchen 
Federal Republic of Germany 
Tel: 89-903-88-06 

Fax: 89-904-35-26 


Italy 

Luigi Rancati 

Rancati Advertising 
Milano San Felice Torre 5 
20090 Segrate, Italy 

Tel: 02-70300088 

Telex: 328601 RANCAD | 
Fax: 39-270300074 


Japan 

Toshio Egusa 
PubliNetwork 
C407, 2-22-6 
Tsukuda Chuo-ku 
Tokyo 104, Japan 
Tel: 03-3536-5404 
Fax: 03-3536-5490 


Southeast Asia 
Taiwan/Hong Kong/Korea/ 
China/Thailand/Philippines/ 
India/Pakistan/Singapore/ 


Malaysia/Indonesia/Australia/ 


New Zealand 

Tom Gorman 

CCl Asia-Pacific, Ltd 

Suite 905, Guardian House 
32 Oi Kwan Rd, Happy Valley 
Hong Kong 

Tel: 833-2181 

Fax: 834-5620 


Dual-port VMEbus/VSB memory 
with Error Detection and Correction, 
single-bit error detection/correction, 
double-bit error detection, 4MB up 
to 64MB in one VMEbus/VSB slot 


COMPUTER DESIGN (ISSN-0010-4566) is published monthly by PennWell Publishing Company, 1421 S Sheridan, 
Tulsa, OK 74112. Second-class postage paid at Tulsa, OK 74112 and additional mailing offices. Editorial offices are 
located at One Technology Park Dr, PO Box 990, Westford, MA 01886. Subscription Prices: Free to design and 
development qualified engineers and engineering managers in the U.S. and Canada. Paid to all others. Qualified 
engineers and engineering managers outside the U.S. and Canada - air shipped - $85 one year. For non-qualified 
recipients in the U.S. - $88 one year, in all other countries - air shipped - $154 one year. Call (918) 832-9263 for subscription 
information. Microfilm copies of COMPUTER DESIGN may be purchased from University Microfilms, a Xerox Company, 
300 N Zeeb Rd, Ann Arbor, MI 48106. POSTMASTER: Send change of address form to COMPUTER DESIGN, Circulation 
Department, PO Box 3466, Tulsa, OK 74101. ©1992 COMPUTER DESIGN by PennWell Publishing Company. All rights 
31312 Via Colinas, Suite 108 | reserved. No material may be reprinted without permission from the publisher. Officers of PennWell Publishing 

= Company: Frank T. Lauinger, Chairman and Chief Executive; Joseph A. Wolking, President and Chief Executive Officer, 
Westlake Village, CA 91362 | pair! Senior Paapee cites Carl J. Lawrence, Senior piece Vv. ich Manty, Vice-President/Finance; W. Steve 


TEL: (818) 991-2254 FAX: (818) 991-3490 || Zimmerman, Vice-President/Corporate Services. 
CALL TOLL FREE: (800) 468-0736 


CIRCLE NO. 94 


e Chrislin Industries, Inc. 


RADISYS GIVES VME 
THE INSIDE 
ADVANTAGE 


EMBEDDED pc @ ATTACHED PC 


EPC Embedded PCs Mass Storage Modules 
EPConnect 
Software 


1 


EPC MODEL EPC-1 EPC-3 | EPC-4 | EPC-5 
| (shipping since Aug '88) | (shipping since Aug ‘89 shipping e Mar ‘90 shipping since Oct ‘9 

Processor Modules: 
CPU 80386 80386SX 80386 80486 
CPU Clock 16 or 2OMHz 16MHz | 25 MHz 25 or 33 MHz 
DRAM 1 or 4 MBytes 1,2 or 4 MBytes 4, 8 or 16MBytes 4, 8 or 16 MBytes 
Graphics | EGA (640 x 350) | VGA (800 x 600) VGA (800 x 600 VGA (800 x 600) 

2 = —— = | ik 
Mass Storage Modules: 
Hard Disk Capacity 40 MBytes 40, 100 or 200 MBytes 
Floppy Drive Size/Cap | 3.5"/ 1.44 MBytes | 3.5” / 1.44 MBytes 
Expansion Capabilities: | | 
PC Add-in Cards | Yes 
EXMbus Expansion N/A 
Software Support: | EPConnect development F 
Copyright © 1989 RadiSys Corporation. All rights reserved. Rad nd EP( 4 tra 7 
RadiSys Corpo 386 and are trade of Intel Corpc Bus 
UNIX is a trademark of American Telephone and Te 


The Intel Inside logo is a trademark of Intel Corporation 


CIRCLE NO. 82 


Integrating a PC with your VME system is 
a smart move. The “PC advantage” provides 
a superior human interface and access to 
the PC’s huge base of system, application 
and development software. 


The PC Advantage belongs inside your 
VME system. Not attached to it. By embed- 
ding a PC inside your VME card cage, 
instead of attaching it externally, you break 
through the inherent communications 
bottleneck that constricts system perfor- 
mance. You also eliminate the superfluous 
hardware and software needed to attach 
two system architectures. 


Only RadiSys EPC® Embedded PCs 
completely integrate the strengths of PC 
and VME. An EPC, with its exclusive 
EPConnect™ Software, is the only 386- or 
486-based, PC-com- 
patible computer with 
software that inte- 
grates the VMEbus into 
the DOS, Windows, 
UNIX and OS/2 envi- 
ronments. EPCs give 
your VME systems: 

* Highest system performance from the real- 
time responsiveness of the direct 32-bit 
interface between the 386 or 486 and the 
VMEbus. 

* Improved system packaging in 1/10th the 
volume, with integral VME ruggedness, and 
no bus link baggage. 


SURROGATE. 
CONTROLLER 


And EPCs cost you less. EPC-based systems 
avoid the costly pitfalls of attached PC 
systems. No extra interfaces, cables, surro- 
gate controllers, or the software to make 
them work. 


Give your VME systems the EPC advan- 
tage. Call (800) 950-0044. We'll send all 
the details. No strings attached. 


THE INSIDEADVANTAGE 


RadiSys Corporation 

15025 SW Koll Parkway 
Beaverton, OR 97006 USA 
(800) 950-0044 

(503) 646-1800 

Fax (503) 646-1850 


10 BREAK SPEED RECORDS, TURN TO THE SRAM LEADER. 


To break performance records, you need extraordinarily fast SRAM solutions. According to In-Stat, Inc., no U.S. 
company sells more SRAM parts worldwide than Cypress. Period. 
eure If you need high-performance SRAMs, this broad range of fast memories is at your service. CMOS or BiCMOS, TTL 
or ECL, from 64-bit to multi-megabit, multichip modules, from standard SRAM pinouts to specialty dual-ports, FIFOs, 
or Cache SRAMs, we've got your high-speed SRAM solution. Our Data Book will show you. It’s a hit. And it’s free. 


FREE 1992 DATA BOOK HOTLINE: 1-800-852-1810* 
Ask for wii C115. 


In Europe c lept. at 1 (415) 961-4201 or ca 
301 North First 


Pav